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Xilinx Advanced Embedded Systems Hardware and Software Design ONLINE

Training duration: 5 sessions


PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.

It covers the same scope and content as a scheduled in-person class and delivers comparable learning outcomes. Daily sessions comprise 4-6 hours of class contact time.


This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system using the Zynq® System on Chip (SoC) processing system (PS).

Hands-on labs & demonstrations provide experience with:

  • Developing, debugging, and simulating an embedded system
  • Utilizing memory resources
  • Implementing high-performance DMA
  • Improving designs by using the Vivado IP Integrator
  • Demo boards in which designs are downloaded and verified
  • Implementing an effective Zynq SoC boot design methodology
  • Creating an FSBL image for flash
  • Utilizing advanced Arm® Cortex®-A9 processor services
  • Analyzing the DMA controller in the Zynq SoC
  • Examining the various library services for peripherals such as Ethernet and USB controllers

The course builds on the skills gained in Embedded Systems Design, using materials developed by Xilinx, and conveniently combines:

Who should attend?

Hardware, firmware, and system design engineers who are interested in Xilinx embedded systems development flow and Software design engineers interested in fully using the Zynq extensible processing platform

Pre-requisites
  • Embedded Systems Design course or experience with embedded systems design and Xilinx EDK toolse
  • Completion of FPGA Essentials training course or equivalent knowledge of Xilinx Vivado Design Suite software implementation tools
  • C or C++ programming experience (including general debugging techniques)
  • Working knowledge of the Zynq SoC (Arm Cortex-A9 processor) or Zynq UltraScale+ MPSoC processors (Cortex-A53 or Cortex-R5 processors).
  • Some HDL modelling experience
  • Conceptual understanding of embedded processing systems including device drivers, interrupt routines writing / modifying scripts, user applications and boot loader operation
  • Experience developing software for embedded processor applications
Software Tools
  • Vivado Design or System Edition (latest version). Please contact Doulos about your specific requirements.
Hardware
  • Architecture: Zynq-7000 SoC, Zynq UltraScale+ MPSoC*
  • QEMU emulator and demo board (used in demonstrations) Zynq-7000 SoC ZC702 or ZedBoard.
  • This course focuses on the Zynq-7000 SoC or Zynq UltraScale+ MPSoC processor architectures. (Zynq UltraScale+ MPSoC designs target QEMU rather than a specific board)

* This course focuses on the Zynq SoC architecture. Please contact Doulos for the specifics of the in-class lab board or other customizations.

Skills gained

After completing this training, you will be able to:

  • Assemble an advanced embedded system
  • Take advantage of the various features of the Zynq SoC, or Zynq UltraScale+ MPSoC processors, including the AXI interconnect, and the various memory controllers
  • Apply advanced debugging techniques, including the use of the Vivado logic analyzer tool for debugging an embedded system and HDL system simulation of processor-based designs Identify the steps involved in integrating a memory controller into an embedded system using the Cortex processors
  • Integrate an interrupt controller and interrupt handler into an embedded design
  • Design a flash memory-based system and boot load from off-chip flash memory
  • Implement an effective Zynq SoC boot design methodology
  • Create an appropriate FSBL image for flash
  • Identify advanced Cortexâ„¢-A9 processor services for fully utilizing the capabilities of the Zynq SoC
  • Analyze the operation and capabilities of the DMA controller in the Zynq SoC
  • Examine the various Standalone library services and performance capabilities of the Ethernet and USB controllers in the Zynq SoC
  • Describe the Standalone library services available for low-speed peripherals that are contained in the Zynq SoC PS
Course Outline

Session 1

  • Overview of Embedded Hardware Development {Demo} Provides an overview of embedded hardware development
  • Hardware-Software Flow {HW Lab 1} Illustrates how design information generated during the hardware development process is moved into the SDK tool realm
  • Zynq-7000 SoC Architecture Overview {HW Lab 2, Demo} Overview of the Zynq7000 SoC architecture
  • Zynq UltraScale+ MPSoC Architecture Overview {HW Lab 4, Demo} Overview of the Zynq UltraScale+ MPSoC architecture
  • Debugging
    • Hardware Introduction {Demo} - Introduces the need and offers a solution for in-chip testing of hardware designs.
    • Hardware - Marking Nets {HW Lab 5} - Reviews the process of marking nets to show which signals should be monitored without having to explicitly instantiate ILA cores.
    • Hardware-Software Co-Debugging (Cross-Triggering) {Demo} Describes how to enable events in hardware to pause the software execution and breakpoints in software to cause an ILA trigger
  • Memory Types
    • Memory Overview - Provides a brief overview of the different types of memory available, as well as when one type of memory would be selected over another.
    • Block RAM Controllers - Introduces two versions of block RAM controllers and how and why they are needed.
    • Static Memory Controllers - Discusses static memory controllers in general and the SMC implementation in the Zynq-7000 family of devices.
    • DDRx Memory Operation - Provides additional details regarding how DDRx memory interfaces with a controller.
    • Dynamic Memory Controller (Zynq-7000 Device) - Covers how the DMC is implemented as well as many of its key behaviors.

Session 2

  • Interrupt Concepts
    • Introduction to Interrupts - Introduces the concept of interrupts, basic terminology, and generic implementation.
    • Interrupts and the Zynq-7000 Device - Presents the details of how the Zynq-7000 platform uses interrupts from both a hardware and software perspective.
    • General Interrupt Controller - Introduces the general interrupt controller (GIC), its features, and some examples of its use.
  • AXI Concepts
    • AXI Streaming: Introduction - Provides the context and background for the streaming configuration of the AXI protocol. 
    • AXI Streaming FIFO - Introduces the AXI Streaming FIFO and its capabilities. 
    • Connecting AXI IP - Focuses on the relationships between different types of AXI interfaces and how they can be connected to form hierarchies. 
    • DMA - Introduces various IP that supports DMA and DMA-like functionality. 
    • Zynq-7000 Device PS-PL Interface- Discusses the various connection points between the PS and PL.

Session 3

  • Zynq-7000 Device PS-PL Interface– Discusses the various connection points between the PS and PL. 
  • Utility Logic – Covers the IP that provides basic logic support within the block design. 
  • Sharing PS Resources (Hardware Perspective) {Lab 9} – Illustrates from the hardware design perspective how a master in the PL can leverage resources within the PS.
  • Multi-Processor Hardware Architecture – Addresses some of the mechanisms that a designer can leverage to support cross-processor communications. 
  • Caching – Introduces the concept of caching and describes how this technique is implemented using the Xilinx processor systems. 
  • Processor Caching and SCLR – Introduces the concepts behind processing caching and the System-Level Control Register. 
  • Accelerator Coherency Port – Describes the purpose and general behavior of the accelerator coherency port (ACP).
  • PS Peripherals
    • High-Speed Peripherals: Gigabit Ethernet – Introduces the Gigabit Ethernet high-speed peripheral.
    • High-Speed Peripherals: USB – Introduces the USB high-speed peripheral.
    • Low-Speed Peripherals: Overview – Introduces the low-speed peripherals in the Zynq All Programmable SoC.
    • Low-Speed Peripherals: UART – Introduces the UART low-speed peripheral.
    • Low Speed Peripherals: CAN – Introduces the CAN low-speed peripheral.
    • Low-Speed Peripherals: I2C – Introduces the I2C low-speed peripheral.
    • Low-Speed Peripherals: SPI – Introduces the SPI low-speed peripheral.
    • Low-Speed Peripherals: SD/SDIO – Introduces the SD/SDIO low-speed peripheral.
    • Utility Logic - Covers the IP that provides basic logic support within the block design. 
    • Sharing PS Resources (Hardware Perspective) {Lab 9} - Illustrates from the hardware design perspective how a master in the PL can leverage resources within the PS.
    • Multi-Processor Hardware Architecture - Addresses some of the mechanisms that a designer can leverage to support cross-processor communications. 
    • Caching - Introduces the concept of caching and describes how this technique is implemented using the Xilinx processor systems. 
    • Processor Caching and SCLR - Introduces the concepts behind processing caching and the System-Level Control Register. 
    • Accelerator Coherency Port - Describes the purpose and general behavior of the accelerator coherency port (ACP).

Session 4

  • Booting
    • Flow {Lecture} Provides a low-level view of the booting process
    • PL {Lecture, SW Lab 3} Introduces the concepts behind configuring the PL at boot
    • Flash Image Generation - Introduces the Flash Image Generator tool, which is used to collect up a variety of files and order them properly in the Flash so that the FSBL can correctly read them. 
    • QEMU: Introduction {Demo} - Introduction to the Quick Emulator, which is the tool used to run software for the Zynq device when hardware s not available.
    • Overview {Lecture, Lab 1} Introduces the main points to how booting a processor is handled in Zynq devices processors
    • Boot Memory Technologies {Lecture} Introduces the main points of the memories that can be booted or executed from
    • PS Processors {Lecture } Introduces the concepts behind a single-core boot, a dual-core boot, and symmetric or asymmetric processing
    • Secure Boot {Lecture} Introduces the concepts behind secure booting
    • FSBL {Lecture, Demo} Introduces the First Stage Boot Loader (FSBL).
    • NEON Co-Processing {Lecture} Introduces the concepts behind the NEON co-processor

Session 5

  • DMA
    • Introduction and Features {Lecture}- Introduces the direct memory access controller
    • Block Design and Interrupts {Lecture} Introduces the DMA block design and the DMA interrupts
    • Read and Write {Lecture} Introduces the concepts behind DMA reading and writing

High-Speed Peripherals

    • Gigabit Ethernet {Lecture, SW Lab 5} Introduces the Gigabit Ethernet high-speed peripheral
    • USB {Lecture} Introduces the USB high-speed peripheral
  • Low-Speed Peripherals
    • Overview {Lecture } Introduces the low-speed peripherals within Zynq
    • UART {Lecture, Demo} Introduces the UART low-speed peripheral
    • CAN {Lecture} Introduces the CAN low-speed peripheral
    • I2C {Lecture} Introduces the I2C low-speed peripheral
    • SPI {Lecture} Introduces the SPI low-speed peripheral
    • SD/SDIO {Lecture} Introduces the SD/SDIO low-speed peripheral
Lab Descriptions
  • Lab 1: Building a Complete Embedded System – Develop hardware that incorporates IP cores to interface to push buttons, a rotary switch, LEDs, an LCD display and serial communication. Use the SDK development tools to create an embedded software application project for the hardware built.
  • Lab 2: Debugging Using the ChipScope Pro Analyzer – Perform simultaneous hardware and software debugging with the ChipScope™ Pro Analyzer, SDK Debug perspective (GDB) and XMD.
  • Lab 3: Extending Memory Resources – Use XPS to extend the memory resources for the Cortex-A9 processor.
  • Lab 4: High-Performance DMA – Apply advanced PL design techniques for adding and connecting custom peripherals that access DDRx memory.
  • Lab 5: Boot Loading from Flash Memory – Develop an application that is stored in flash memory, load it through a boot loader program and execute a software application from external memory.
  • Lab 6: Simulating an Embedded Processing System – Set up and perform HDL-based simulation on a design that contains an embedded processor system. Explore the tool flow for performing embedded processing simulation, including hardware co-simulation.
  • Lab 7: Zynq Boot Memory Lab – Explore the principles of creating a bootable flash image based on a First Stage Bootloader (FSBL) project.
  • Lab 8: Configuring DMA on the Zynq SoC – Program the DMA controller on the Zynq PS and explore the various Standalone library services that support the Zynq PS DMA controller.
  • Lab 9: Peripheral Programming on the Zynq SoC – Program the Gigabit Ethernet controller on the Zynq SoC and verify in hardware. Explore the various lwip Standalone library services that support the Zynq Gigabit Ethernet controller.

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