This course introduces new and experienced designers to the most sophisticated aspects of the UltraScale™ architecture. Targeted towards designers who have used the Vivado® Design Suite, this course focuses on designing for the new and enhanced resources found in Xilinx® UltraScale FPGAs.
Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.
In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.