Xilinx Partial Reconfiguration Tools and Techniques

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who want to learn partial reconfiguration techniques

Vivado Design or System Edition 2019.1

• Architecture: UltraScale and 7 series FPGAs*
• Demo board: Kintex® UltraScale FPGA KCU105 board, Kintex-7 FPGA KC705 board, and ZedBoard**

* This course focuses on the UltraScale and 7 series architectures. Check with Doulos for the specifics of the in-class lab board or other customizations.

** The UltraScale architecture versions of the "Using the PRC IP in a Partial Reconfiguration Design" lab and the "Using ILA Cores to Debug Partial Reconfiguration Designs" lab are not available because of QSPI and PRC issues on the KCU105 board. These two labs support only the 7 series architecture. The "Partial Reconfiguration in Embedded Systems" lab requires a ZedBoard for implementation.

Day 1

Day 2

• Lab 1: Partial Reconfiguration Tool Flow – Illustrates the basic Vivado Design Suite Partial Reconfiguration flow. At the completion of this lab, you will download a partial bitstream to the demo board via the JTAG connection.
• Lab 2: Partial Reconfiguration Project Flow – Illustrates Partial Reconfiguration (PR) project flow in the Vivado Design Suite. At the end of this lab, you will be able to create multiple RMs and configurations using Partial Reconfiguration Wizard.
• Lab 3: Floorplanning the PR Design – Illustrates how to create efficient Pblocks for a Partial Reconfiguration design. At the end of this lab, you will understand the impact of the SNAPPING_MODE property for a Pblock.
• Lab 4: Using the Partial Reconfiguration Controller in a PR Design – Illustrates using the PRC IP and hardware triggers to manage partial bitstreams.
• Lab 5: Partial Reconfiguration Timing Analysis and Constraints – Shows how area groups and Reconfigurable Partitions affect design performance.
• Lab 6: Partial Reconfiguration in Embedded Systems – Illustrates implementing PR designs in an embedded environment.
• Lab 7: Debugging a Partial Reconfiguration Design – Demonstrates using ILA cores to debug PR designs and shows which signals to monitor during debugging.