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This course is available Live Online worldwide: View the Live Online full course description »
Limited In-Person schedule available in Europe from March 2021
Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who want to learn partial reconfiguration techniques
Vivado Design or System Edition 2019.1
* This course focuses on the UltraScale and 7 series architectures. Check with Doulos for the specifics of the in-class lab board or other customizations.
** The UltraScale architecture versions of the "Using the PRC IP in a Partial Reconfiguration Design" lab and the "Using ILA Cores to Debug Partial Reconfiguration Designs" lab are not available because of QSPI and PRC issues on the KCU105 board. These two labs support only the 7 series architecture. The "Partial Reconfiguration in Embedded Systems" lab requires a ZedBoard for implementation.
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