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FPGA Acceleration of Convolutional Neural Networks

1 hour session (All Time Zones)
Presenter: John Aynsley

Co-Founder and Technical Fellow
Presenter: Hardus Richter

Asia and Europe

Time: 10-11am (GMT) 11am-12pm (CET) 3.30-4.30pm (IST)


Time: 10-11am (PST) 11am-12pm (MST) 12-1pm (CST) 1-2pm (EST)

With demand growing for applications (from image recognition to data analysis) requiring machine or deep learning in more and more industries, both in the cloud and at the edge, this webinar aims to help you understand the advantages and challenges of implementing neural networks on an FPGA from first principles.

John Aynsley of Doulos will introduce the webinar and provide an overview of the essential concepts of neural networks, convolution operations and model training that you need to understand.

Hardus Richter of ASIC Design Services will then explore the considerations and challenges of CNN quantization and FPGA accelerator design in more depth.

What you will learn:

  • the principles of neural networks and convolution operations
  • the essentials of CNN quantization
  • FPGA accelerator design considerations

The webinar also presents the applicability of quantization and accelerators to the Vitis AI tools from Xilinx.

The session will last for about one-hour, and will be interactive with Q&A participation (supported by Doulos & ASIC Design Services) for attendees.

John Aynsley

John Aynsley is Co-Founder and Technical Fellow at Doulos. John will introduce the training webinar and provide an overview of the important concepts behind Convolutional Neural Networks.

Hardus Richter

Hardus Richter is a Machine Learning Engineer for ASIC Design Services. Hardus will co-present the webinar particularly covering quantization of CNNs and FPGA accelerator design.

Attendance is free of charge

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