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Maximize Design Productivity using Vivado with SystemVerilog

Wednesday November 18 2020

1 hour session (All Time Zones)
Presenter: Mike Smith

Specialist Xilinx Trainer

Asia and Europe

Wednesday, November 18, 2020

Time: 10-11am (GMT) 11-12pm (CST) 3.30-4.30pm (IST)


Wednesday, November 18, 2020

Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)

Webinar Overview:

Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to FPGA hardware designers. We explore the features of SystemVerilog that are useful for RTL synthesis using the Xilinx® Vivado® Design Suite, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.

We start from the basic principles of RTL coding style in SystemVerilog, then focus on the language features that allow FPGA hardware designers to work very efficiently while at the same time avoiding synthesis pitfalls.

Content Summary:

  • Introduction
  • SystemVerilog in the Vivado Design Suite
  • Modules, ports, parameters, and hierarchy
  • Testbenches
  • Combinational and clocked logic
  • Assignments and procedures
  • Control constructs and operators
  • Hardware-oriented data types including packages
  • Interfaces and Modports

Mike Smith

Mike Smith Specialist Xilinx Trainer, will be presenting this training webinar, which will consist of a one-hour session and will be interactive with Q&A participation from attendees.

Attendance is free of charge

If you have any queries, please contact

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