The FPGA Section
The words FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device) are everywhere nowadays. Not just for systems that actually need to be re-programmed in the field, but for any application that can't justify the up-front expense of an ASIC.
Doulos works closely with our partners and leading technology vendors to train engineers in FPGA applications. This includes routine support for Actel, Lattice, Altera, and Xilinx technologies on our VHDL courses as well as dedicated FPGA training classes.
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Knowhow FPGA Resources
Bookmark this page to follow our latest developments!
- See below for a great selection if FPGA Hints, Tips, and Tricks
- Recent article Using SystemVerilog for FPGA Design
- Check out our FPGA Technotes
- Visit the video gallery for "ARM Cortex-M1 for FPGAs"
- Tales from the Helpdesk - find out about our great post-course support below
FPGA Hints, Tips, and Tricks
This section of the website is dedicated to programmable logic devices - the 4 Ts... Tools, Technology, Tips, Tricks.
Organising a collection of tips like this can be tricky! So if you cannot find what you want, just use the Search box at the top right of the page. You'll find that information is linked from different places in the list below - for instance setting generics on parameterised designs using Xilinx ISE can be accessed from the Tools, Technology, or Tips links depending on whether you look for Xilinx ISE (a Tool), Xilinx (a technology) or setting parameters (a Tip).
One other note: although many of these examples use VHDL, they often apply equally well to Verilog - it's just that in our training experience, the majority of FPGA/CPLD users are using VHDL.
- Setting generics/parameters in Mentor Precision
- Setting generics/parameters in Altera Quartus II
- Setting generics/parameters in Xilinx ISE
- Setting generics/parameters in Actel Libero
- Setting generics/parameters in Lattice ispLever
- Setting generics/parameters in Synplicity Synplify
- Controlling Xilinx ISE with Tcl
- Controlling Altera Quartus II with Tcl
- Controlling Actel Designer with Tcl
- Compiling Simulation Libraries
- Why didn't Xilinx accept my Offset Out or Offset In constraint?
- Why should I care about Transparent Latches?
- I'm using a Black Box and the place and route tool fails - why?
- Partial Reconfiguration of Xilinx FPGAs
- Automating tool flows with Tcl scripts
- Settings Generics/Parameters for Synthesis
- How do I know I got transparent latches - and why do I care?
- Why didn't my Finite State Machine (FSM) optimization work?
- What does library 'X' do?
- Why can't I simulate my clock circuit?
- The golden rules of debugging
- Detecting events that are shorter than your clock period
- Synchronisation and edge-detection
- Using SystemVerilog for FPGA Design
Tales from the Helpdesk
- Counting Short Pulses
Detecting events that are shorter than your clock period. VHDL and Verilog code available.
- Implementing Large Multiplexers
Issues in large multiplexer structures.
- Cleaning Dirty Signals
Producing a nice clean input signal from a messy source. VHDL and Verilog code available.
- Synchronisation and Edge-Detection
A discussion of the issues and some suggestions for solutions. VHDL and Verilog code available.