Doulos, the global leader for the development and delivery of design and verification training solutions, has launched the first dedicated public training class offering a one-stop solution for new SystemVerilog users and evaluators.

Comprehensive SystemVerilog is the first training course to cover both design and verification methodology in a single class. By addressing SystemVerilog methodology as a whole, delegates gain a more coherent understanding of the language and its capabilities and how it can be fully exploited within the design flow. Furthermore the repetition of topics, which is inevitable with classes that deal with design and verification separately, is avoided.

Although presented from a vendor independent perspective, which makes Comprehensive SystemVerilog particularly attractive to evaluators, Doulos has worked exceptionally closely with leading vendors in the SystemVerilog space. As a result, delegates are able to explore SystemVerilog during the workshops using a range of EDA tools - including Mentor Graphics Questa™Sim, Synopsys VCS® and Design Compiler®.

The 5-day Comprehensive SystemVerilog comprises:

• Fundamentals of SystemVerilog
• Assertion-based Verification using SystemVerilog
• SystemVerilog Testbench Automation

Public classes are available in the USA and Europe. The class caters for engineers from a VHDL or Verilog background.

Comprehensive SystemVerilog is part of the wider Doulos SystemVerilog portfolio, which has been created to meet the needs of design teams with mixed backgrounds or team-based requirements. Modular SystemVerilog offers a menu of customizable training modules to enable fine tuning for in-house or team-dedicated delivery.

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