Hands-on tutorial to be given at D*A*TE 2002, Palais des Congres, Paris, March 5th 9 - 12.30. Registration information is given at the bottom of the page.

System level technologies over recent years have moved on from ASICs and ASSPs to SoC level integration. This stepwise increment in chip complexity requires an equivalent shift in design methodology. Design exploration for SoC designs requires a system-level modeling language to provide a reference model of the whole system at an abstract level accompanied with fast simulation speeds. Mixed-language system level design flows (e.g. C++/HDL) don't allow rapid exploration of the design space or a unified specification and modelling language.

There is an obvious advantage in the use of a single language for the system level model, which can also describe IP blocks, system hardware and software, and easily move functionality between these domains to obtain the best partition from numerous alternatives.

SystemC is an open-source system-level modeling language based on C++ which extends the language with constructs for system-level design to express hardware and software modules. The SystemC design flow starts from a highly abstract algorithmic system description and applies an iterative refinement process. Details regarding algorithm partitioning, timing, process scheduling, data representation, hardware and software partitioning are progressively added. Changes in model behaviour can be obtained against the original reference algorithm and corrective measures can be applied.

The language allows a clear separation between system tasks and communication between those tasks such that the description of modules can be detached from inter-module communications. In general, common SoC platforms are made up of modules such as CPU cores, memories, and peripheral hardware interconnected via a system-level communication channel, the system bus. SystemC can abstract details of implementation-specific interfaces between modules and the system bus using SystemC channel constructs. These abstract channels can then be refined to a cycle accurate level once an implementation is chosen. During this process, decisions have to be made by the designer concerning module partitioning to obtain a good fit between the specification and target platform.

The hands-on workshop will take the participants through a complete platform-based design from behavioural and IP descriptions to hardware synthesis with the use of SystemC and the CoCentric SystemC Compiler. The example platform-based design contains a risc microprocessor, a DSP unit, memory, buses and peripheral interfaces. The design is progressively moved from a purely abstract level to a hardware and software platform-specific implementation. The design flow is illustrated, showing the exploration of design alternatives at high levels of abstraction, and the consequences of selecting a given hardware / software partition.

The tutorial introduces some key guidelines that the system-level designer can use to approach the SystemC design flow and the SystemC language elements which support modelling at the appropriate level of abstraction.

Topics presented will include:

• The SystemC design flow.
• SystemC levels of abstraction.
• Describing hardware with modules & processes.
• Interface abstraction using channels.
• Simulation & debugging with SystemC.
• Hardware / software partitioning.
• Model refinement for synthesis.
• Scheduling & scheduling constraints. RTL synthesis.