Global training solutions for engineers creating the world's electronics
1 hour session (All Time Zones)
Presenter: Doug Smith
Time: 10-11am (GMT) 11-12pm (CET) 3.30-4.30pm (IST)
Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)
We know formal can prove things, but where do we apply it? Did you know you can use formal to generate simulation testbenches for covering coverage holes or have it visualize your design without writing a single line of testbench code?
Formal can be used for identifying metastability, X propagation, fault propagation and detection, equivalence, and so much more.
In this webinar, we'll have a look at the many ways formal helps out your design verification process, including the use of complexity analysis and bounded reachability analysis, overconstraining the design, setting cut points, and creating abstractions.
Some examples will be demonstrated using the Jasper Formal Verification Platform by Cadence.
Attendance is FREE and live Q&A will be provided throughout the broadcast.
Doug Smith - Doulos Senior Member Technical Staff will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.
Attendance is free of charge
If you have any queries, please contact webinars@doulos.com
Visit www.doulos.com/knowhow
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.
