Global training solutions for engineers creating the world's electronics
1 hour session (All Time Zones)
Presenter: Doug Smith
Time: 10-11am (BST) 11-12pm (CEST) 2.30-3.30pm (IST)
Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)
In the world of formal verification, abstractions along with design reductions, help reduce the state space and make it easier for formal to converge on its proofs.
In this webinar Doulos Senior Member Technical Staff, Doug Smith will explore the process of abstraction, safe design reductions, and when to use them. Doug will show practical examples of both (using VC Formal from Synopsys) and discuss how to interpret formal results obtained by using abstractions and reductions.
The content will be useful to anyone who wants to learn to make more effective use of formal.
Attendance is FREE and live Q&A will be provided throughout the broadcast.
Doug Smith - Doulos Senior Member Technical Staff will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.
Attendance is free of charge
If you have any queries, please contact webinars@doulos.com
Visit www.doulos.com/knowhow
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.
