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Xilinx Training Location Details

Directions from San Jose Airport
Directions from San Francisco Airport
Hotel Information

Class Times

Classes are normally run in training room LC5 between 9am and 5pm

Address of Xilinx Training Venue

Xilinx Headquarters:
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124-3400
Street View / Bing Maps / Mapquest

Please use visitor car parking in front of Building 4 and register with security at least 10 minutes before the course start time.

Directions from San Jose Airport

Take Airport Blvd to Coleman Ave signal light.
Turn left and stay in RIGHT HAND LANE.
Enter freeway 880 South (to the right).
Take 85 South to Gilroy.
Exit Union Avenue. Turn LEFT at stop light.
Turn LEFT at Union Avenue
Turn LEFT at Logic Drive

Directions from San Francisco Airport

Take 101 south (San Jose)
Take Hwy 85 South (Gilroy)
Exit Union Avenue. Turn LEFT at stop light.
Turn LEFT at Union Avenue
Turn LEFT at Logic Drive

Alternative route from San Francisco Airport

Take 101 North (San Francisco)
Take 380 junction (San Jose)
Exit 280 South to San Jose
Take Hwy 85 South (Gilroy)
Exit Union Avenue. Turn LEFT at stop light.
Turn LEFT at Union Avenue
Turn LEFT at Logic Drive

Hotel Information

For your convenience here is a list (in no particular order) of hotels in the vicinity. Please don't forget to request the Xilinx rate at the time of booking.

Pruneyard Inn ( 2.5 miles, 5 min), 408-559-4300
Toll House (5.0 miles, 10 min), 408-395-7070
Campbell Inn (2.6 miles, 6 min), 408-374-4300
Carlyle Hotel (1.6 miles, 3 min), 408-559-3600
Los Gatos Lodge (3.3 miles, 7 min), 408-354-3300
Larkspur Landing - Campbell (3.8 miles. 11 min), 408-364-1514

Upcoming Live Webinars

Designing with AMD Kria SOMs

Tuesday December 17 2024

1 hour session (All Time Zones)

This webinar will walk through the design process for using AMD Kria SOMs, including the use of Vivado and Vitis.

C/C++ Memory Management: Design and Debugging

Wednesday December 18 2024

1 hour session (All Time Zones)

This webinar explores best practices for avoiding memory issues in design and debugging memory usage issues in C and C++.

Signal Integrity PCB Vias and Remedies

Wednesday January 15 2025

30 minute session (All Time Zones)

This webinar will explore the effects of routing vias and connector plated through holes on very high data rate signals using actual test results from as-built PCBs.

Edge Machine Learning - Project Tips & Tricks

Friday January 17 2025

1 hour session (All Time Zones)

This webinar will provide some useful directions for incorporating machine learning within your next embedded project.