Global training solutions for engineers creating the world's electronics

Xilinx Training Location Details

Class Times

Classes are normally run in training room LC5 between 9am and 5pm

Address of Xilinx Training Venue

Xilinx Headquarters:
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124-3400
Street View Bing Maps Mapquest

Please use visitor car parking in front of Building 4 and register with security at least 10 minutes before the course start time.

Directions from San Jose Airport

  • Take Airport Blvd to Coleman Ave signal light.
  • Turn left and stay in RIGHT HAND LANE.
  • Enter freeway 880 South (to the right).
  • Take 85 South to Gilroy.
  • Exit Union Avenue. Turn LEFT at stop light.
  • Turn LEFT at Union Avenue
  • Turn LEFT at Logic Drive

Directions from San Francisco Airport

  • Take 101 south (San Jose)
  • Take Hwy 85 South (Gilroy)
  • Exit Union Avenue. Turn LEFT at stop light.
  • Turn LEFT at Union Avenue
  • Turn LEFT at Logic Drive

Alternative route from San Francisco Airport

  • Take 101 North (San Francisco)
  • Take 380 junction (San Jose)
  • Exit 280 South to San Jose
  • Take Hwy 85 South (Gilroy)
  • Exit Union Avenue. Turn LEFT at stop light.
  • Turn LEFT at Union Avenue
  • Turn LEFT at Logic Drive

Hotel Information

For your convenience here is a list (in no particular order) of hotels in the vicinity. Please don't forget to request the Xilinx rate at the time of booking.

  • Pruneyard Inn ( 2.5 miles, 5 min), 408-559-4300
  • Toll House (5.0 miles, 10 min), 408-395-7070
  • Campbell Inn (2.6 miles, 6 min), 408-374-4300
  • Carlyle Hotel (1.6 miles, 3 min), 408-559-3600
  • Los Gatos Lodge (3.3 miles, 7 min), 408-354-3300
  • Larkspur Landing - Campbell (3.8 miles. 11 min), 408-364-1514

Upcoming Live Webinars

Image 1

Modern C++ Casts: How and When to Use Them

Wednesday February 12 2025

1 hour session (All Time Zones)

The casting data conversion process in C++ is often misused. This webinar highlights common errors and how and when to use casts effectively in your projects.

Register Now

Image 1

What Can Formal Do for Me?

Friday February 14 2025

1 hour session (All Time Zones)

This webinar will look at the ways formal helps your design verification process, including complexity analysis, bounded reachability analysis, overconstraining the design, setting cut points, and creating abstractions.

Register Now

Image 1

Extending a Yocto BSP using Layers

Wednesday February 26 2025

1 hour session (All Time Zones)

We will investigate how the Yocto build environment provides the initial components to successfully boot a Linux system and how it can be modified to manage challenging requirements in your projects.

Register Now

Image 1

Rapid Creation of Edge AI Solutions on an FPGA

Friday February 28 2025

1 hour session (All Time Zones)

This webinar will explore ideas on identifying and deploying trained AI models on FPGAs and look at contemporary software tools and APIs which help in putting together an FPGA-based Edge AI solution.

Register Now

Image 1

Accelerating Formal Verification Using Non-Determinism

Wednesday March 26 2025

1 hour session (All Time Zones)

This webinar will explain what non-determinism is, how it's used, and show lots of examples so you can take advantage of non-determinism to accelerate the verification of your designs.

Register Now