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Clock Domain Crossing
1 hour session (All Time Zones)
Presenter: Charles Gardiner
Time: 10-11am (GMT) 11-12pm (CET) 3.30-4.30pm (IST)
Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)
The primary goal in safely implementing any IC or FPGA project is to achieve a synchronous design. This implies that the relationship of all clocks and asynchronous resets to each other is defined in the synthesis constraints. Incorrect handling of clock-domain crossing (CDC) is probably the primary cause of sporadic errors, which are impossible to catch in a digital simulation and can cause a system to inexplicably fail in the field.
This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.
Topics include:
The webinar will also feature a working example from Microchip® using PolarFire® FPGAs and SoCs and the Libero® SoC Design Suite.
Charles Gardiner - Doulos Certified Training Instructor - will be presenting this training webinar, which will consist of a one-hour session and will be interactive with Q&A participation from attendees.
Attendance is free of charge
If you have any queries, please contact webinars@doulos.com
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Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.
