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How to accelerate both your FPGA application and productivity
1 hour session (All Time Zones)
Presenter: L. Eric Culverson
Time: 10-11am (BST) 11am-12pm (CEST) 2.30-3.30pm (IST)
Time: 10-11am (PDT) 11am-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)
By utilizing modern co-synthesis methodologies, system-level software can be made to run as customized hardware modules within an FPGA-based hardware kernel, running seamlessly with the rest of the application software on heterogeneous processors integrated utilizing the AMD Vitis™ Unified Software Development environment.
With the advent of heterogeneous compute platforms and the requirement for edge to cloud scalability, an easy-to-navigate, multi-capable design methodology is needed.
In this webinar:
We will show you the Vitis-based design methodology that seamlessly utilizes various compilers and analysis tools to support both proprietary and industry-standard libraries/APIs, thereby offering a structured approach for all aspects of software development, debug and deployment for individual kernels and complete systems.
What you will learn:
L. Eric Culverson - AMD Authorized Training Instructor of Technically Speaking, Inc - will present this webinar, with interactive Q&A for attendees throughout.
Attendance is free of charge
If you have any queries, please contact webinars@doulos.com
Visit www.doulos.com/knowhow
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.
