What is the difference between VHDL and Verilog?
Fundamentally speaking, not a lot. You can produce robust designs and comprehensive test environments with both languages, for both ASIC and FPGA. However, the two languages approach the task from different directions; VHDL, intended as a specification language, is very exact in its nature and hence very verbose. Verilog, intended as a simulation language, it much closer to C in style, in that it is terse and elegant to write but requires much more care to avoid nasty bugs. VHDL doesn't let you get away with much; Verilog assumes that whatever you wrote was exactly what you intended to write. If you get a VHDL architecture to compile, it's probably going to approximate to the function you wanted. For Verilog, successful compilation merely indicates that the syntax rules were met, nothing more. VHDL has some features that make it good for system-level modelling, whereas Verilog is much better than VHDL at gate-level simulation. To confuse the situation more, see SystemVerilog...
Can I use VHDL for the analog part of a design?
Yes and No. Yes, there is a VHDL Analogue and Mixed Signal language (VHDL-AMS), based on VHDL 93, which allows modelling of both analogue and digital in the same language. You can see our 2-4 day VHDL-AMS workshop syllabus on our training page. However the idea of analogue synthesis is still in its early days, so currently you wouldn't normally be able to go on and synthesize an analogue model written in VHDL-AMS.
How must I write VHDL to make it synthesisable?
Because large parts of the language make no sense in a hardware context, synthesisable VHDL is a relatively small subset of VHDL. You must stick to this subset, and understand exactly how the synthesis tool you use interprets that code. For FPGA in particular you must also develop a good understanding of the structure of your chip, and know how your code must reflect the most efficient use of that structure. Fundamentally, never forget that you are designing a circuit, not writing a program. Forgetting this simple but important fact will only lead to pain later.
How many versions of VHDL are there?
There are five. The original release of the VHDL language occured in 1987 with the adoption of the Language Reference Manual as an IEEE standard. In 1993, the IEEE-1076 standard was modified and ratified and became known as VHDL'93. This is now widely supported. In 2000, the VHDL 1076 2000 Edition appeared - this fixed shared variables by introducing the idea of protected types. Next, VHDL 1076-2002 appeared. This includes protected mode types, but also changes ports of mode buffer to make them more usable, along with some other small changes. VHDL 1076-2008 is the latest revision of the standard, issued in January 2009. It makes extensive additions, changes and improvements including fixed and floating point packages, records and arrays with unconstrained elements, new types, new and enhanced operators, enhanced bit string literals, and better printing to name just a few. In practice, VHDL 1076-1993 is the current flavor of VHDL which is widely supported by tool vendors. VHDL 1076-2008 support is continuously being added to vendor tools, so check the tool documentation and release notes for the latest information.
Is VHDL going to be developed further?
You might have heard a lot about System Verilog, and wondered if VHDL is going to also be developed? There is an activity to develop an improved VHDL, and VHDL-2008 was released in January 2009. You will find more information here.
A VHDL design can be moved to any tool or technology. Right?
On the face of it, this is true. VHDL was designed to be and is a technology independent design language. However, there is less of a compliance issue between different simulators than there is for synthesis tools. Generally speaking, moving VHDL code from one simulator to another involves one or two minor changes to the VHDL. Two different synthesis tools may have broad agreement of what constitutes sythesisable code, but may interpret that code in different ways. This is particularly an issue for us at Doulos in developing our training courses, because we like to present a reasonably generic approach to writing VHDL for synthesis. This means that the VHDL we teach you is guaranteed to be more transportable between synthesis tools than it otherwise would be. Our pain is your gain! In addition, because we are so aware of the differences between synthesis tools this means that we emphasise the best way of writing VHDL to get the best from your synthesis tool. For FPGA, code that uses one technology in the most efficient way is unlikely to be as efficient when sythesised to a different device family.
Are there any tools to generate VHDL test benches automatically?
The basic answer is no. Writing a testbench can be a complex task, and can be more complex than the design being tested. If you mean "Can I get a code framework for a simple testbench", then a number of tools provide simple "testbench templates"; even the Emacs editor VHDL mode can do this! For more advanced ways of writing testbenches, you might want to look at the so-called "Testbench Automation" languages, such as SystemVerilog and SystemC Verification Library. This involves learning another language of course. If you want to know how to write more complex testbenches (for instance to cope with data arriving in a different order from the order it entered a device), have a look at our Expert VHDL Verification course.
Can you give me a measure of the productivity improvements I should expect from VHDL?
Well, do you believe the hype! Yes, ultimately there are considerable productivity gains to be had from using high-level design techniques in conjunction with synthesis technology, providing that your designs are: complex, amenable to synthesis, not dependent upon the benefits of a particular technology.
Obviously, complex means different things to different people, but a good rule of thumb is that complex means the implementation part of the design process is considerably more awkward than the specification phase. Let's face it, if the specification phase is significantly longer than the implementation phase, you need to put effort here, not into High Level Design (HLD). Of course, once you are benefiting from HLD productivity gains, the specification phase becomes more significant. OK, that's HLD: VHDL is a HLD design entry language, so we would expect the use of VHDL with synthesis technology to improve productivity in the design process. However, you won't get those benefits immediately. Your first VHDL-based project will probably take slightly longer than if you had used your previous design process. Where you really win out is second time around. In order to reduce the time spent on your first project and to ensure that subsequent projects benefit from good VHDL design practices, you need to ensure that your engineers are well trained (well, we would say that wouldn't we!).
I can see how to write abstract behavioural descriptions in VHDL, but how do you describe and simulate the actual hardware?
This is probably the biggest hurdle that many hardware engineers face when moving to VHDL. After all, sometimes we need to be able to describe actual implementation as well as abstract functionality. The way to describe "physical" hardware in VHDL is to write VHDL models of those components. This is supported in VHDL through the use of instantiation. VHDL does not allow you to physically simulate your hardware. You can only simulate a model of that component in a VHDL simulation. Historically, gate-level simulation using VHDL has been notoriously slow. This led to the creation of the 1076.4 working group to provide a mechanism to allow faster gate-level simulation using VHDL. Their effort became known as the VITAL standard. VITAL is not a VHDL issue for you, but an EDA vendor/ASIC supplier issue. A simulator is VITAL compliant if it implements the VITAL package in its kernel (this is faster than simulating the VITAL primitives in the VITAL package). You don't need to change your VHDL netlist; your ASIC vendor needs to have a VITAL compliant library though, in order for you to take advantage of the simulation speed up. Thus the ASIC vendor's library elements need to be implemented entirely in VITAL primitives. Note that many companies use Verilog for gate-level simulations as it is still faster than VHDL, even with the improvements from VITAL. The reason is that Verilog was designed from the start as a gate-level simulation language.
I've heard that VHDL is very inefficient for FPGAs. Is that true?
It might be. If the code in question was written with no thought for how the FPGA would implement the circuit, then it's entirely possible that it was inefficient. If the code is written with consideration of the FPGA resources available and the synthesis tool being used, then no, it's not inefficient.
Are there any VHDL source code libraries available to save me having to re-invent common code fragments and functions?
There are a few libraries available for most levels of VHDL design. The IEEE library contains very low-level type-and-function packages. The std_logic_1164 package is an industry standard, and practically every piece of VHDL you ever write will use this package; the types std_logic and std_logic_vector are the overwhelmingly dominant types for anything related to digital design. For arithmetic, numeric_std (from the same IEEE library) is a collection of functions that work on std_logic and its derivatives.
Are freeware / shareware VHDL tools available?
There are a few; generally these are limited in some way (for instance they have no graphical interface, or simulate only certain sizes of model). The VHDL FAQ part 3 has a section on free tools.
Are there any inexpensive VHDL tools available?
Yes, there are one or two. The main FPGA vendors including Altera and Xilinx provide simple toolsets, including a VHDL simulator. These toolsets are normally limited to small devices, and will also have a limit on the number of lines of code you can write; and of course the target technology for synthesis is fixed to a particular manufacturer's chips.
What is Synthesis?
Synthesis is the stage in the design flow which is concerned with translating your VHDL code into gates - and that's putting it very simply! First of all, the VHDL must be written in a particular way for the target technology that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.
How about on-line information resources?
You're already here! Try the Models section of our VHDL Designer's Guide for examples of VHDL models and assorted tips and tricks.
E-mail us if you have a question you would like added to this list - send email
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