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January 2019|News
(Please note the following links have now expired)
Doulos have a strong presence at DVCon in San Jose, February 22-25, participating in two half-day tutorials and three regular papers. Check out the details below:
Tutorial - Advanced Verification Techniques Using VMM. Doug Smith of Doulos leads a great team of experts presenting an in-depth tutorial which includes real-world examples of best-practice VMM usage. Attendees will get the know-how needed to begin using the latest features in their own projects.
Tutorial 1 (Session 20); Monday February 22, 1.30 - 5.00pm
Tutorial - The OSCI TLM-2.0 Standard and Synthesis Subset. John Aynsley Doulos CTO, Michael Meredith of Forte Design Systems and Michael McNamara of Cadence explore the lessons learned from the practical adoption of the TLM-2.0 standard, the resulting resurgence of SystemC synthesis, and the synergy between the two
Tutorial 2 (Session 21); Monday February 22, 1:30 - 5:00pm
Paper - SystemVerilog Meets C++: Re-use of Existing C/C++ Models Just Got Easier.
Presenter: John Aynsley
Session 4.1; Wednesday February 24, 11.00am - 12.30pm
Paper - Asynchronous Behaviors Meet Their Match with SystemVerilog Assertions
Presenter: Doug Smith
Session 11.2; Thursday February 25, 1.30 - 3.00pm
Paper - Functional Coverage - without SystemVerilog!
Presenter: Doug Smith
Session 13.1; Thursday February 25, 1.30 - 3.00pm
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