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Creating UVM Components from MATLAB Models and SystemVerilog-DPI

Friday November 07 2025

30 minute session (All Time Zones)
Presenter: Dr David Long

Doulos Principal Member Technical Staff

Asia and Europe

Friday, November 07, 2025

Time: 10-11am (GMT) 11-12pm (CET) 3.30-4.30pm (IST)


Americas

Friday, November 07, 2025

Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)


Webinar Overview:

Many chip designs contain blocks with functionality originally developed as algorithmic models in tools such as MATLAB. When it comes to verification of RTL blocks (or even the complete chip) in an HDL simulator, a reference model to check for correct operation is essential. The reference model is also invaluable for developing and debugging the verification environment for the design.

Today, most verification engineers’ language of choice is SystemVerilog, using UVM to create reusable verification components, environments and tests. Creating a reference model for a SystemVerilog UVM checker from scratch can be time-consuming and error-prone – making use of the algorithmic model could alleviate these issues. The SystemVerilog Direct Programming Interface (DPI) provides a simple mechanism to call compiled C code within a UVM component. MathWorks tools can generate SystemVerilog and UVM components from MATLAB and Simulink models that use this DPI approach.

In this webinar, we will start by reviewing the UVM features and architecture requirements for typical use-cases. We will then take a closer look at the SystemVerilog DPI and show how it can be used within UVM sequences and components. The main body of the presentation will walk through the steps required to generate a reusable UVM checker from a simple MATLAB/Simulink model, including:

  • How to generate UVM code for a required coding style
  • The use of parameters and the UVM configuration database
  • Use of generated components within the UVM environment
  • Running a simulation and checking the results

This webinar will be of interest to verification engineers wishing to learn how SystemVerilog DPI can be used to import reference models and stimulus generators from MATLAB (or other similar environments) into UVM and to MATLAB/Simulink users who need to provide reference models to their RTL verification team.


Dr David Long

Dr David Long - Doulos Principal Member Technical Staff - will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.


Attendance is free of charge

If you have any queries, please contact webinars@doulos.com


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