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PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE. Please note for this course, daily sessions are up to 7 hours including breaks.
This training course is ideal for engineers involved in developing software for platforms powered by the Arm® Cortex®-A5 application processors.
The learning is reinforced with unique Lab exercises which are run inside a self contained virtual machine environment. This allows the student to experience a real-life and project-ready development environment without the complexity of installing complex software prior to the class. This virtual machine is for the student to keep after the training class, allowing you to further experiment with embedded software development once the class has come to completion.
This course is aimed at software developers writing low level and bare-metal code for Armv7-A processors, concentrating on the Cortex-A5 processor, and at operating system developers who need to understand the details of the Arm v7A processors' architecture.
Delegates should have some understanding of embedded programming in C and assembler. Knowledge of other processors is a benefit but is not strictly required for attending this class.
This class uses training materials developed by Arm® and is complemented by Doulos' own lecture and laboratory material. This offers the students a well rounded and practical view of the topics covering both the processor's features along with how to program it.
Architecture versions • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions • Pipelines
Arm RealView Developer Suite • Tool Licensing • GNU and ABI • Debug Interfaces
Load/Store Instructions • Data Processing Instructions • Flow Control • Miscellaneous • DSP
Exceptions overview • Interrupts sources and priorities • Abort Handlers • SVC Handlers • Undef Handlers • Reset Handlers
Cache basics • Caches on Arm processors • Tightly Coupled Memory (TCM) • Optimization consideration
Memory Management Introduction • Access Permissions and Types • Memory Protection Unit (MPU) • Memory Management Unit (MMU) • Optimizations & Issues
Why do we need synchronization? • Synchonization primitives • SWP instruction • LDREX and STREX instructions
Overview • Level 1 memory system
MPCore Features • Snoop Control Unit • Accelerator Coherency Port (ACP) • Interrupt Controller • Timer and watchdog • TrustZone Support • Developing for Arm MPCore Processors • Booting SMP • Configuring an interrupt • Synchronization
NEON Instruction Set Overview • NEON Software Support
Processor Power Consumption • Power Modes • NEON and MPCore
Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data issues
Linking Basics • System and User Libraries • Veneers and Interworking • Linker Optimizations and Diagnostics • Arm Supplied Libraries
Mixing C/C++ and Assembler • Stack Issues • VFP/NEON • Advanced Building Facilities • Embedded Software Development
An "Out-of-the-box" build • Tailoring the C library to your target • Tailoring image memory map to your target • Reset and Initialization • Further memory map considerations • Building and debugging your image
Debug Logic Overview • Debug Logic Features • Tools use of Debug Logic • Trace Logic Overview • Debug vs. Trace • System Level Debug Infrastructure • CoreSight Introduction • CoreSight Debug • CoreSight Trace
Exception Handling • Memory System • Debug • Software
The learning is reinforced with practical exercises using the GCC software development tool chain and covers advanced topics such as Arm/Thumb2 assembly, writing low level device drivers, exception handlers and linker scripts.
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