Arm Cortex-A9 for Zynq System Design

• Engineers who wish to become skilled in the use of a Cortex-A9 based System On Chip from a software and verification perspective
• Engineers who need to understand integration details centered around the AXI protocol
• Engineers who will required to provide a software solution to bring a bare metal Cortex-A9 MPCore system to life

• The hardware structure of a Zynq™ device
• The details of a Cortex-A9 processor core
• The details of the MPCore logic
• Memory management for Arm v7 based devices
• AXI system interfaces
• Bringing up a bare metal system

Delegates should have some knowledge of embedded systems and a basic understanding of embedded programming in C and assembler. Knowledge of earlier Arm architectures is an advantage but not required. 

C Programming for Embedded Systems training is also available from Doulos.

A carefully crafted combination of content from Arm, AMD and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.

• Zynq SoC System Architecture
• Embedded Systems Hardware and Software Design

Introduction to Zynq

• Architecture details with Cortex-A9 MPCore implementation choices
• Core and FPGA interfaces
• Processing System Built-in Peripherals
• Memories and Memory Controllers
• FPGA logic and rooting details
• I/O Peripherals
• Processor System Boot Options
• Cortex-A9 core building blocks
• Private peripherals
• Snoop control unit
• Accelerator coherency Port (ACP)
• Generic interrupt controller
• Core system interfaces

Introduction to the Arm v7 instruction set architecture

• Arm v7 Unified Assembly Language

Hands-on Lab session

• Assembly Language Basics
• Assembly Language Data Processing

Caches

• Cache basics
• Caches on Arm processors
• Optimization consideration

Exception Handlers for Arm application processors

• Exceptions overview
• Interrupts sources and priorities
• Abort Handlers
• SVC Handlers
• Undef Handlers
• Reset Handlers

Hands-on Lab session

• Exceptions Handling
• Peripherals Driver Design

Memory Management

• Memory Management Introduction
• Access Permissions and Types
• Memory Protection Unit (MPU)
• Memory Management Unit (MMU)
• Optimizations & Issues

Using the NEON co-processor

• NEON Instruction Set Overview
• NEON Software Support

Writing C for Arm

• Parameter Passing
• Floating Point Linkage
• Alignment
• Coding Considerations

Synchronization Support

• Synchronization primitives
• SWP Instruction
• LDREX / STREX and CLREX Instructions

Embedded software development

• An out-of-the-box” build
• Tailoring the C library to your target
• Tailoring image memory map to your target
• Reset and Initialization
• Further memory map considerations
• Building and debugging your image

Software Engineer's Guide to Zynq

• Zynq Peripherals
• Cortex-A9 Pipeline
• Media Processing Engine
• Register Renaming
• Fast Loop Mode
• Program Flow Prediction
• Preformance Monitoring Unit
• Level One Memory System

MPCore Logic

• MPCore Features
• Snoop Control Unit
• Accelerator Coherency Port (ACP)
• Interrupt Controller
• Timer and watchdog
• TrustZone Support
• Developing for Arm MPCore Processors
• Booting SMP
• Configuring an interrupt
• Synchronization

TrustZone Overview

• Exception Handling
• Memory System
• Debug
• Software Implementation

 

Appendix

Linker & Libraries Hints & Tips

• Linking Basics System and User Libraries
• Veneers and Interworking
• Linker Optimizations and Diagnostics
• ARM Supplied Libraries

 

AXI Protocol

• Main Features
• AXI Channels
• AXI Transactions
• Ordering Capabilities

The learning is reinforced with unique Lab Exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.

Lab exercises for assembly programming cover the concepts of data transfer, data processing, flow control and DSP instructions, and rely on the default development tool-set offered by Xilinx as well as a remote debug session based on a combination of GDB and the Zynq QEMU platform used for fast prototyping.

Additional exercises show the main steps involved in bringing a bare metal system to life, including the configuration of the various mode stacks and the creation of an interrupt handler. These exercises make use of the assembler and linker as well as the interactive debugger (GDB/DDD and QEMU).