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Arm Cortex-M0+ System Design
Arm® Cortex®-M0+ System Design is a 3-day class for software/hardware and verification engineers developing or supporting Cortex-M0+ based Systems on Chips. The course covers the Arm Cortex-M0+ programmer's model, instruction set architecture as well as hardware intergration, system interfaces, power management and debug infrastructure.
Design teams working on the integration and verification of an Arm Cortex-M0+ based core.
This class uses training materials developed by Arm®
Introduction to Arm
Cortex-M0+ Overview
Tools Overview for Arm Microcontrollers
Toolchain • Models • Debug & Trace • Development Boards
v6-M Programmer’s Model
Data types • Core registers • Modes • Exceptions • Instruction • Set Overview
v6-M Memory Model
System Caches • Write Buffers • TCMs • Memory Types • Endianness • Address Map
v6-M Exception Handling
Exception Model • Interrupts • Interrupt Handling • Prioritization and Control • Writing the Vector Table and Interrupt Handlers • Internal Interrupts and RTOS Support • Fault Exceptions
v6-M Compiler Hints and Tips
Basic Compilation • Compiler Optimizations • Coding Considerations • Mixing C/C++ and Assembler • Local and Global Data issues
CMSIS Overview
CMSIS-CORE • CMSIS-DSP • CMSIS-RTOS • CMSIS-SVD • CMSIS-DAP
SysTick Timer
Built-in Functions • Calibration Examples
AMBA AHB-Lite
AHB Evolution • AHB-Lite Bus Protocol • AHB Signals
Processor Core
Processor Pipeline • Instruction Execution
System Interfaces
Memory System Bus Interfaces Details • Processor and Integration Levels
Integration Example
Wake-up Interrupt Controller • Debug Access Port • Micro Trace Buffer • Clock Gating
Power Management
Architectural Clock Gates • Sleep Modes • Power Domains • System Control
Cortex-M0+ Debug
Introduction to Debug • Debug Access Port (DAP) • Breakpoints/Watchpoints & Vector Catch • Cortex-M0+ Debug • System Control
Memory Protection
Memory Types • Memory attributes • Memory Protection Regions Configurations
Trace
MTB Operations • Register Description • Signal Description • Implementation Issues
Implementation and Integration
RTL Configuration • Design Flow Step • Reference Methodologies Arm and Cortex-M0+ are registered trade marks of Arm Holdings Plc.
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