This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers. Key areas focused on:
- Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources.
- Describing improvements to the dedicated transceivers and Transceiver Wizard.
- Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities.
- Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado™ Design Suite.