Training Duration: 5 sessions (6 hours per session)
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
Course Description
Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as Adaptable Engines, high-speed I/O, clocking, Scalar Engines, Intelligent Engines, and the programmable network on chip (NoC). Also learn how to use leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. Within this course you will use different AMD Versal adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application partitioning, design closure, power, and thermal solutions to enhance the performance of a design.
The emphasis of this course is on:
- Reviewing the architecture of the Versal adaptive SoC
- Describing the different engines available in the Versal architecture and what resources they contain
- Describing the architectures of the network on chip (NoC) and AI Engine
- Outlining the memory solutions and programming interfaces available in the Versal adaptive SoC
- Identifying the PCI Express® and serial transceiver solutions available in the Versal adaptive SoC
- Demonstrating the embedded software development flow for Versal devices
- Using the provided design tools and Versal adaptive SoC design methodologies to create complex systems
- Leveraging the Power Design Manager (PDM) tool for power estimation
- Performing system-level simulation and debugging
- Improving Versal adaptive SoC system performance
- Identifying Versal adaptive SoC power and thermal solutions.
Software and hardware developers, system architects, DSP users, and anyone who wants to learn about the architecture of the Versal adaptive SoC and related design methodologies.
- Basic knowledge of AMD FPGAs and adaptive SoCs
- Basic knowledge of the VivadoTM and VitisTM tools
- Vivado Design Suite
- Vitis unified software platform
- PetaLinux Tools
Architecture: AMD Versal Adaptive SoCs
After completing this comprehensive training, you will have the necessary skills to:
- Describe the Versal adaptive SoC architecture
- Identify the different engines available in the Versal devices and what resources they contain
- Utilize the hardened blocks available in the Versal architecture
- Describe the NoC and AI Engine architectures
- Outline the memory solutions and programming interfaces available in the Versal adaptive SoC
- Identify the PCI Express and serial transceiver solutions available in the Versal adaptive SoC
- Follow the high-level system migration recommendations provided in this course
- Describe the embedded software development flow for Versal devices
- Use the provided design tools and Versal adaptive SoC design methodologies to create complex systems
- Leverage the Power Design Manager (PDM) tool for power estimation for Versal devices
- Describe the different debugging options available for the Versal adaptive SoC
- Perform system-level simulation and debugging
- Identify Versal adaptive SoC power and thermal solutions.
Course Outline Part-1: Designing with the Versal Adaptive SoC: Architecture
- Introduction
Describes the need for Versal devices and offers an overview of the Versal portfolio. {Lecture}
- Architecture Overview
Provides a high-level overview of the Versal architecture, illustrating the various engines available in the Versal architecture. {Lecture}
- Design Tool Flow
Maps the various engines in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab}
- Adaptable Engines (PL)
Describes the logic resources available in the Adaptable Engine. {Lecture}
- SelectIO Resources
Describes the I/O bank, SelectIOTM interface, and I/O delay features. {Lecture}
- Clocking Architecture
Discusses the clocking architecture, clock buffers, clock routing, clock management functions, and clock de-skew. {Lecture, Lab}
- Processing System
Reviews the Arm® Cortex®-A72 processor APU and Cortex-R5 processor RPU that form the Scalar Engine. The platform management controller (PMC), processing system manager (PSM), I/O peripherals, and PS-PL interfaces are also covered. {Lecture}
- PMC and Boot and Configuration
Describes the platform management controller, platform loader and manager (PLM) software and boot and configuration. {Lecture, Lab}
- DSP Engine
Describes the DSP58 slice and compares the DSP58 slice with the DSP48 slice. DSP58 modes are also covered in detail. {Lecture, Lab}
- AI Engine
Discusses the AI Engine array architecture, terminology, and AIE interfaces. {Lecture, Lab}
- NoC Introduction and Concepts
Covers the reasons to use the network on chip, its basic elements, and common terminology. {Lecture, Lab}
- Memory Solutions
Describes the available memory resources, such as block RAM, UltraRAM, LUTRAM, embedded memory, OCM, and DDR. The integrated memory controllers are also covered. {Lecture}
- PCI Express & CCIX
Provides an overview of the CCIX PCIe module and describes the PL and CPM PCIe blocks. {Lecture, Lab}
- Serial Transceivers
Describes the transceivers in the Versal device. {Lecture}
- System Migration
Compares the various functional blocks of the Versal devices to previous-generation devices. Describes the migration of designs from the UltraScaleTM and UltraScale+TM architectures to the Versal architecture. {Lecture}
Course Outline Part-2: Designing with the Versal Adaptive SoC: Design Methodology
- Board System Design Methodology
Describes PCB, power, clocking, and I/O considerations when designing a system. {Lecture}
- Embedded Software Development
Describes the software development environments and embedded software development flows for Versal devices. Also introduces embedded software debugging. {Lecture, Lab}
- Software Build Flow
Provides an overview of the different build flows, such as the do-it-yourself, Yocto Project, and PetaLinux tool flows. {Lecture, Lab}
- Software Stack
Reviews the Versal device bare-metal, FreeRTOS, and Linux software stack and their components. {Lecture}
- Security Features
Describes the security features of the Versal devices. {Lecture}
- Application Partitioning 1
Covers what application partitioning is and how the mapping of resources based on the models of computation can be performed. {Lecture}
- Power Design Manager
Discusses using the new Power Design Manager tool, including import and export functions. {Lecture, Lab}
- Hardware, IP, and Platform Development Methodology
Describes the different Versal device design flows and covers the custom platform creation process using the Vivado IP integrator, RTL, HLS, and Vitis environment. {Lecture, Lab}
- System Integration and Validation Methodology
Describes different simulation flows as well as timing and power closure techniques. Also explains how to improve system performance. {Lecture}
- Configuration and Debugging
Describes the configuration and debug process for the Versal devices. Also covers the Versal device debug interfaces, such as the test access port (TAP) and debug access port (DAP) controller. {Lecture}
- Overview of HSDP
Describes the high-speed debug port (HSDP) in the Versal device. Also goes over the steps to use the SmartLynq+ module for high-speed debugging. {Lecture, Lab}
- System Simulation
Explains how to perform system-level simulation in a Versal device design. {Lecture, Lab}
