Designing with Intel Quartus Prime

Existing users who wish to become more productive by extending their knowledge of Quartus Prime and exploiting the latest features and techniques. 

Design engineers who are new to Quartus Prime, and want quickly to get fully up to speed with all the key features of Quartus Prime. Please see the pre-requisites below. 

Not sure how much training you need? 
Looking to attend specific modules? 
Please contact your local Doulos team to discuss your requirements.

Part of a team? 
On-site training is also available to optimize the course to your precise needs, experience, and project context.

• Digital and FPGA Design competence
• A prior knowledge of Verilog or VHDL languages is expected but not compulsory

In addition for the Advanced module: 

• Solid background on Static Timing Analysis using Intel Timing Analyzer and experience with Quartus Prime and its features (or previous appropriate training - for example: prior attendance of days 1-2).

Please discuss your experience with Doulos prior to booking.

Part 1 - Essentials

• How to take advantage of the powerful and rich Intel FPGA Design Tools and environment: The Intel® Quartus® Prime Software Suite
• Mastering the numerous tools and the rich design flow that's essential to designing and debugging Intel FPGAs efficiently
• The essential concepts of Timing Constraints and Timing Analysis.

Part 2 - Advanced

• Mastery of the timings aspects of FPGA Design:
  • Timing Constraints
  • Timing Exceptions
  • Timing Optimization Techniques
  • Synopsys Design Constraints (SDC)
  • Source-Synchronous Interfaces
  • Feedback Design
  • Timing Analysis and Tcl (optional)

The course is applicable to all versions of Intel Quartus Prime.

Appropriate topics are followed by practical hands-on exercises.

Please contact Doulos to book the full training course or to discuss which module is best suited to your individual or team's requirements.

DAYS 1-2: DESIGNING WITH INTEL QUARTUS PRIME - ESSENTIALS

Designing with Quartus Prime - Design Flow basics, scripting & STA fundamentals (Day 1)

• Introduction to Intel® Quartus® Prime software
  Intel Quartus software versions : Lite vs Std vs Pro.
  Design Flow. GUI. Resetting the Layout.
• Introduction to Quartus Projects
  Key files. Creating a Project from scratch.
  Design files, default settings and priority.
  Launching the compilation tasks.
• Practical Exercise 1 (Optional)
• Quartus design flow and compilation tips
  The complete design flow and tools.
  Processing options, Managing the messages: the Message Suppression Manager.
  Compilation reports.
• Practical Exercise 2 – part 1
• Static Timing Analysis fundamentals
  Introduction to Timing Analysis and SDC Language.
  Timing Analysis Basics.
  Synchronous and Asynchronous analyses.
  Introduction to the industry-standard Synopsys Design Constraints (SDC) language.
  SDC Survival Guide for “Must Know” constraints, often sufficient for simple designs.
• Practical Exercise 2 – part 2
• Advanced Quartus Project management
  Project Archive & Restore.
  Project Cleanup.
  Project Revisions ! (an essential feature). Creating and comparing revisions.
  The Viewers: RTL, technology Map, Post-Layout, State Machines
  DRC : the Design Assistant
  The Advisors.
• Practical Exercise on FPGA board
• Design Flow Automation - Scripting
  For improved productivity and quality, design tasks and project management can be automated and
  secured with command-line scripts and Tcl scripts: Project creation, file management, archival,
  cleanup, compilation, bitstream creation, FPGA configuration, & programming, result testing, etc.
• Optional Exercise

Designing with Quartus Prime - Real-time Debugging, Timing Analyzer & Design Analysis (Day 2)

• In-System Memory Contents Editor + In-System Sources & Probes.
  Two very useful tools, free and easy to use.
  Control and monitor the inside of your FPGA in real time, interactively, all through the JTag connection.
  Concept, Applications, How-To.
• Practical Exercise on FPGA board
• SignalTap
  Embedded Real Time Logic Analyzers to debug your design in real time.
  Concepts, use cases, applications, limitations.
  Storage modes, triggering, sampling, storing.
  Creating the Embedded Logic Analyzer, implementation, preparation/configuration, compilation.
  Static and dynamic configuration.
  How-Tos.
  Viewing Real Time captures of State Machines.
• Practical Exercise on FPGA board
• Advanced SignalTap
  Advanced Features of Signal Tap for more complex designs and situations :
  - Storage Qualifier,
  - State-Based Trigger flow,
  - Mnemonic Tables
  - PowerUp Trigger,
  Tapping from Technology Map Viewers.
  Scripting.
• End of previous Signal Tap exercise.
• Introduction to Intel Timing Analyzer
  The Timing Analyzer always runs, during P&R and at the end of compilation to create sign-off reports !
  Launching Timing Analyzer in interactive mode
  Timing Analyzer GUI, the panes and their functions
  The SDC constraints (text) editor, templates and interactive constraints composition
• Timing Analyzer Design Flow
  Netlist generation
  Constraints entry
  Activate the constraints in the project
  Full Compilation
  Post-compilation reports and analysis
• Practical T-A Exercise 1
• Timing Analyzer Reports
  Creating the reports
  - Summary
  - Detailed
  - Advanced reporting

DAYS 3-4: DESIGNING WITH INTEL QUARTUS PRIME - ADVANCED

Designing with Quartus Prime - Timing Constraints Fundamentals & Advanced (Day 3)

• Timing Constraints - Clocks
  Reminder about SDC Netlist terms
  Using the Name Finder - Finder Filters and examples
  - Base Clocks,
  - PLLs
  - Generated Clocks
  - Virtual Clocks.
  - Clock Uncertainty, Jitter analysis.
  Reporting and checking clocks constraints.
• Practical T-A Exercise 2
• Timing Constraints - I/Os and Synchronous Interfaces
  Constraining Combinatorial interfaces,
  Constraining System Synchronous Inputs and Outputs
  I/Os Minimum and Maximum Delays,
  Virtual Clocks,
  Pin Load and Advanced I/O Timings,
  Reporting IO Timings.
• Practical T-A Exercise 3
• Timing Exceptions – False paths & Clock groups
  False Paths Logic-based and Timing-based
  Re-Synchronizers
  Clock Groups
  Clock Muxing
  Reporting Exceptions
• Timing Exceptions – Multi-cycle Paths
  -Multicycle Logic to open the window
  -Window shifting
  End Multicycle Setup & Hold (EMS-EMH) constraints
• Optional T-A Exercise 4
• Timing Optimization Techniques
  Reminder about Timing advisor and main Optimization principles.
  Synthesis Options, Timing Driven Synthesis, WYSIWIG Re-synthesis,
  Physical synthesis, Register re-timing, Register duplication. Pros & Cons.

Designing with Quartus Prime - Advanced Timing course (Day 4)

• More on SDC
  Generated clock (by register)
  Clock uncertainty
  Using clock uncertainty for over-constraining
  Reason to use Virtual clocks
  Constraining I/Os, “FPGA-Centric” approach
• Timing Exceptions (advanced)
  Advanced concepts on Multicycles Constraints (Setup, Hold).
  Using Start Multicycle Setup & Hold constraints (SMS,SMH)
  Management of the Timing Exceptions and their Priorities in Timing Analyzer.
  Clock Enables analysis with multicycle, using the Fanout Registers Constraints.
• Additional features for constraining
  Time groups
  Delays and Skew
  set_net_delay
  set_max_skew
• Optional: TQ Advanced Exercise 1
  
• Source-Synchronous Interfaces - SDR
  Introduction to Source Synchronous Interfaces. Concepts and use.
  SDR and DDR schemes, Center-aligned and Edge-aligned.
  SDC Constraints for SDR Source-Synchronous Input and Output Interfaces.
  Different case of analysis (FPGA-centric or Board System),
  Virtual Clocks, PLLs management. Associated Timing Reports.
• Practical Exercise
  
• Source-Synchronous Interfaces - DDR
  SDC Constraints for DDR Source-Synchronous Input and Output Interfaces. Different case of analysis
  (FPGA-centric or Board System), PLLs/DDIO management. Exceptions. Associated Timing Reports.
  Practical Exercise: constraining a DDR Ti ADC interface
  
• Feedback Design
  Concept, analysis and associated constraints, useful to constrain SDRAM, SPI, SSRAM interfaces (for
  example). Clock and Data cases. Associated Timing Reports.
  Example of a Quad-SPI IP.
• Optional: Timing Analysis and Tcl
  Quartus Tcl Packages
  Running TA from command line
  SDC constraints for P&R use only
  Timing Analysis script examples
  Constraining JTag paths