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Intel FPGA Design with Nios II
Intel® FPGA Design with Nios II is a 3-day course aimed at engineers who are using Intel (Altera) technology to design Systems on Programmable Chip.
The course covers both hardware and software aspects of the design flow and is accessible to both hardware and software engineers. This co-training approach enables successful team working on SoPC designs, in that both software and hardware engineers gain an appreciation of the requirements of each other's discipline. This ensures successful convergence in the design flow and the development of efficient architectures.
The scope of the course includes an appreciation of the hardware platform, hardware-software partitioning, hardware acceleration as well as software development and debugging. These concepts are reinforced by numerous and varied practical exercises, using the latest tools and technology, on actual hardware platforms.
Intel FPGA Design with Nios II is developed and maintained for Doulos by specialist partner ALSE based on source material from Intel.
Design engineers who wish to learn how to use Intel technology for Systems on Chip.
All participants must be computer literate and have a basic understanding of digital design. For the first day, a prior understanding of Quartus Prime is preferable, but not mandatory. For the third day, prior experience in C or C++ is preferable, but not mandatory.
Why and when to use SoPC • Introduction to the Nios II processors family and options • Selecting and configuring the Processor, the IPs, the available standard and specific peripherals • The DE0 development Kit • Introduction to the complete Hardware design flow using Qsys and Quartus Prime.
Practical Exercise: Creating a complete SoPC from scratch, tested on the FPGA Kit.
The new device families • General architecture • Hardcore and Fabric dichotomy • Rapid presentation of the ARM Cortex-A9 MP dual core • The SoC FPGA Development Environment.
Concepts • Advantages • Drawbacks • Differences with legacy fabric Builder • How to migrate to Qsys.
Creating the simulation environment • Modeling the Peripherals and the UART • Using ModelSim to simulate the complete SoPC system.
Practical Exercise: RTL Simulation with ModelSim of the SoPC system created previously.
The Fabric • NOC architecture & benefits • The Avalon Interfaces • Miscellaneous kinds of peripheral ports • Transfer and Addressing modes • Generating the Switch Fabric • Adding custom peripherals.
On-chip or Off-chip peripherals • Creating custom peripherals step-by-step • The Component Editor • Using Tcl scripting • _hw.tcl.
Practical Exercise: Design & use of a simple Custom Peripheral (PWM in VHDL).
Motivation and concept of Hardware Acceleration • Limitation of traditional architectures • Using Avalon simultaneous multi-master capabilities and the NOC to optimize the performance • Custom Masters, the DMA engines, building hardware accelerators • Custom Instructions: Principles, advantages, how to design and use them • CRC calculation example • Custom Peripherals for hardware acceleration • C2H: C code To Hardware compiler (Legacy tool).
Practical Exercise: Accelerating CRC calculation using three different methods and comparing the respective results.
Principles • The Altera solution roadmap.
Main concepts • Software aspects • Introduction to Nios II EDS / Eclipse SBT • Creating a software project • Tools for Compilation and Debugging • Project management • Creating a C/C++ application and associated Board Support Package.
Practical Exercise: Creating a Software Project from scratch, testing it on the Hardware.
Motivation • Compatibility with the GUI • Utilities available to automate the creation of proper scripts • Command line configuration & software download.
Practical Exercise: Using the command line flow and scripts.
Introduction to the Hardware Abstraction Layer (HAL) and programming model for standard basic peripherals: System clock, alarm, time-stamp and high-resolution timers • Programming the peripherals • The role of the data cache • Handling custom peripherals.
Practical Exercise: Using the HAL API to exercise PIOs and Timers.
System.h • Updating the hardware configuration • Memory mapping • Stack • Heap • The linker • Mastering the boot sequence (alt_sys_init and alt_main) • Hosted vs Free-Standing, optimizing the code size • HAL and file system • Unix-style functions • The Linker script • Stack & Heap • The Boot sequence • The Boot copier • Hosted vs Free-Standing.
Caveats about legacy interrupts • Presenting the two Interrupts modes and hardware • Pros and Cons of the Cascadable Vectored Interrupt Controller • Using and programming the standard interrupt controller.
Practical Exercise: Enhance the PWM lab to use Interrupts generated by the edge-triggered PIO.
The Optimization flow: Profiling, identifying performance bottlenecks and candidates for hardware acceleration • Using custom instructions • Hardware acceleration through dedicated custom hardware peripherals • Programming API for DMAs, alternative to Altera's API, issues with Data cache • C2H software perspective (Legacy tool)
Practical Exercise: Simple algorithm • Optimized software implementation • Accelerating with a custom instruction • Hardware acceleration with dedicated hardware block and DMA transfers • Accelerating with C2H • Measuring and comparing performance.
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