Familiarity with logic design (state machines and synchronous design)
Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
Vivado® System Edition
Mentor Graphics QuestaSim simulator
Architecture: 7 series FPGAs*
Demo board: Kintex®-7 FPGA KC705 board*
* This course focuses on the Kintex-7 architecture. Please contact Doulos for the specifics of the in-class lab board or other customizations.
After completing this comprehensive training, you will know how to:
Describe and utilize the ports and attributes of the serial transceiver in 7 series FPGAs
Effectively utilize the following features of the gigabit transceivers:
8B/10B and other encoding/decoding, comma detection, clock correction and channel bonding
Pre-emphasis and linear equalization
Use the 7 Series FPGAs Transceivers Wizard to instantiate GT primitives in a design
Access appropriate reference material for board design issues involving the power supply, reference clocking and trace design
7 Series FPGAs Overview
7 Series FPGAs Transceivers Overview
7 Series FPGAs Transceivers Clocking and Resets
8B/10B Encoder and Decoder
Lab 1: 8B/10B Encoding and Bypass
Commas and Deserializer Alignment
Lab 2: Commas and Data Alignment
RX Elastic Buffer and Clock Correction
Lab 3: Clock Correction
Lab 4: Channel Bonding
Transceiver Wizard Overview
Lab 5: Transceiver Core Generation
Lab 6: Simulation
Lab 7: Implementation
Physical Media Attachments
64B/66B Encoding and the Gearbox
Lab 8: 64B/66B Encoding
Transceiver Board Design Considerations
Transceiver Test and Debugging
Lab 9: Transceiver Debugging
Lab 10: IBERT Lab
Lab 11: System Lab
Transceiver Application Examples
Lab 1: 8B/10B Encoding and Bypass - Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.
Lab 2: Commas and Data Alignment - Use programmable comma detection to align a serial data stream.
Lab 3: Clock Correction - Utilize the attributes and ports associated with clock correction to compensate for frequency differences on the TX and RX clocks.
Lab 4: Channel Bonding - Modify a design to use two transceivers bonded together to form one virtual channel.
Lab 5: Transceiver Core Generation - Use the 7 Series FPGAs Transceivers Wizard to create instantiation templates.
Lab 6: Simulation - Simulate the transceiver IP using the IP example design.
Lab 7: Implementation - Implement the transceiver IP using the IP example design.
Lab 8: 64B/66B Encoding - Generate a 64B/66B core by using the 7 Series FPGAs Transceivers Wizard, simulate the design, and analyze the results.
Lab 9: Transceiver Debugging - Debug the transceiver IP using the IP example design and Vivado debug cores.
Lab 10: IBERT Lab - Create an IBERT design to verify physical links.
Lab 11: System Lab - Perform all design steps from planning the design, generating the core, integrating the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.
Looking for team-based training, or other locations?
Complete an enquiry form and a Doulos representative will get back to you.