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Advanced Formal Verification ONLINE

Standard Level - 5 sessions (6 hours per session)


PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE. 

It covers the same scope and content as a scheduled in-person class and delivers comparable learning outcomes.


This is the follow-on course to Essential Formal Verification Online. It is intended to take engineers beyond an introductory use of formal technologies to a deep, practical level of knowledge of formal verification.

Advanced Formal Verification will equip you to tackle complex verification challenges, by taking full advantage of formal verification on your engineering projects.

Advanced topics such as satisfiability, abstractions (e.g., safe, reduction, and induction), formal synthesis, non-determinism, solving inconclusive proofs, interpreting formal coverage, under- and over-constraining, formal equivalency, post-silicon debug, and much more are discussed in depth. While the practical labs are run hands-on using specific formal verification tools, the main focus is on the concepts that are applicable to all of the current commercial formal verification tools.

Workshops comprise approximately 50% of class time and are based around carefully designed hands-on exercises to reinforce learning.

Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported by this course include:

  • Cadence Jasper™ Formal Verification Platform
  • Siemens Questa® Formal
  • Synopsys VC Formal™

This course is targeted at individuals that already have a working knowledge of formal technologies and some hands-on
experience.

It is particularly targeted at engineers and teams who want to move to a subject-matter expert level on formal verification, understanding how to plan, use, and implement formal verification on their real-world projects.

  • Learn the process of analyzing a design project and determining what parts are formal friendly and where to leverage formal or mix with other technologies
  • Learn how to break down a formal problem and solve it with different techniques
  • Learn how to build a formal verification environment
  • Learn advanced SVA syntax and techniques to apply formal to more applications
  • Learn the difference between safety and liveness properties and when to use them
  • Learn about nondeterminism, how it accelerates formal, and how it helps you solve problems
  • Learn the formal abstraction process and practically implement formal abstractions
  • Learn different reduction techniques for improving formal analysis
  • Learn how to package together formal development into a verification IP
  • Understand formal coverage, how to interpret it, and how to merge with other coverage
  • Learn advanced techniques for bug hunting
  • Learn how to constrain formal inputs and avoid over- and under- constraining
  • Learn how to supercharge the formal verification process with formal automations
  • Learn advanced formal techniques and applications like Sequential Logic Equivalency Checking, Post-Silicon debug, etc.

This class assumes a working knowledge of SystemVerilog, SystemVerilog Assertion syntax, and formal verification concepts and tools. We strongly recommend prior attendance of the Doulos Essential Formal Verification Online course (or equivalent) prior to attending this course.

Please contact Doulos directly to discuss and assess your specific experience against the pre-requisites.

Doulos training materials are renowned for being the most comprehensive and user-friendly available. Their style, content and coverage are unique in the training world and have made them sought after resources.

The materials include fully indexed class notes creating a complete reference manual.

How Formal Works

Formal algorithms • Counter-examples •Formal engines • Clocking • Initialization and reset sequences • Formal flow and synthesis • Debugging with formal

Formal Modeling

Formal synthesis • Safety • Liveness • Embedded assertions •Fairness • Formal testbenches • Helper code

Nondeterminism

Free variables • Design symmetry • Data independence • Symbolic constants • Formal testbenches • Formal scoreboarding

Abstractions and Reductions

Complexity in formal • Reduction and safe reduction techniques • The basic abstraction process • Types of abstract models • Design symmetry and data independence • Example of design abstractions • Safe abstractions

Abstract Modeling

Abstract checker models • Abstraction by induction • Abstraction using state machines • Abstraction using events • Data integrity checking • Abstract checker model examples

Constraining Formal

Under constraining • Over constraining • Additional SVA syntax • Advanced property writing • Evaluating constraints

Formal Coverage In-Depth

Types of coverage • Cone of influence • Formal coverage methodology • Interpreting coverage • Merging coverage

Reachability Analysis

Reachability analysis • Applications for reachability • Formal apps using reachability • Proving cover properties • Goal posting • Bounded reachability

Formal Equivalency

Differences between LEC and SEC • How to setup and use SEC • Tips for SEC convergence • Applications for SEC • Data-path equivalency checking

Bug Hunting and Proofs

Simulating reset • Engine switches • Engine monitoring • Case splitting • Helper assertions • Debugging formal results • Handling inconclusives • Bounded proofs • Creating formal target groups • When to switch to simulation

Formal Planning and Process

Formal planning process • Assessing formal readiness • Formal requirements • Formal methodology • Formal goals and sign-off

Formal Sign-off and Post-Silicon Debug

Formal sign-off requirements • Formal coverage metrics • Post-silicon debug

Formal Reuse & IP

Reusing formal artifact • Creating a formal IP • Packaging a formal IP

Formal Automations

The need for formal automation • The Tcl interface • Formal apps and their automations • Linking Python with formal

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