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Common Mistakes in VHDL

1 hour session (All Time Zones)
Presenter: Doug Perry


Asia and Europe

Time: 10-11am (GMT) 11-12pm (CST) 3.30-4.30pm (IST)


Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)

Webinar Overview:

Learning any new programming language will undoubtedly be influenced by your existing design experience, and although that knowledge is largely very useful it can also work against you... For example, when you come to learn VHDL, the parallel nature of the hardware design language might trip you up if you've been using a language that has a sequential nature, such as Java, C or C++.

In this webinar VHDL guru, Doug Perry, (author of "VHDL: Programming by Example") explores some of the common mistakes designers make when starting out with VHDL and provides useful tips and resources for getting on track. Practical examples will be provided using Aldec Riviera-PRO™ in the online simulation environment EDA Playground.

Content Summary:

  • VHDL Statements
  • Process Statements
  • Signal Assignments
  • Delta Delays
  • The Simulation Cycle
  • Variables
  • Incomplete Assignments
  • Unexpected Latches
  • Drivers
  • Types
  • Expressions

Doug Perry

Doug Perry - a VHDL Guru - will present this training webinar, which will consist of a one-hour presentation with interactive Q&A available to attendees throughout.

Attendance is free of charge

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