Global training solutions for engineers creating the world's electronics products

Defining Timing Constraints using SDC

Wednesday September 01 2021

1 hour session (All Time Zones)
Presenter: Johannes Biedermann

Doulos Certified Training Instructor

Asia and Europe

Wednesday, September 01, 2021

Time: 10-11am (BST) 11-12pm (CEST) 2.30-3.30pm (IST)


Americas

Wednesday, September 01, 2021

Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)


Overview

This webinar will help you get started with building timing constraints for your digital design using the industry standard Synopsys Timing Constraints (SDC) format.

As well as getting an overview of what SDC is and the basic terminology, you will learn how to define clocks, how to set up timing for the I/Os and how to define exceptions like false-paths and multicycle-paths; everything you need to set up timing in a simple design.

Content Summary:

- What is SDC, and why is it important?
- SDC Basics
- Defining Clocks
- Defining Interface Timing
- Defining Exceptions


Johannes Biedermann

Johannes Biedermann - Doulos Certified Training Instructor, will be presenting this training webinar, which will consist of a one-hour session, and will be interactive with Q&A participation from attendees.


Attendance is free of charge

If you have any queries, please contact webinars@doulos.com


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