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1 hour session (All Time Zones)
Time: 10-11am (GMT) 11-12pm (CET) 3.30-4.30pm (IST)
Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)
This webinar will help you get started with building timing constraints for your digital design using the industry standard Synopsys Timing Constraints (SDC) format.
As well as getting an overview of what SDC is and the basic terminology, you will learn how to define clocks, how to set up timing for the I/Os and how to define exceptions like false-paths and multicycle-paths; everything you need to set up timing in a simple design.
- What is SDC, and why is it important?
- SDC Basics
- Defining Clocks
- Defining Interface Timing
- Defining Exceptions
The webinar will also feature a working SDC example design by Microchip® applied to a PolarFire® FPGA using the Libero® SoC Design Suite.
Attendance is free of charge
If you have any queries, please contact email@example.com
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.