ARM1176 SoC Design

System design engineers, software design engineers and hardware design engineers who wish to develop systems and applications based on ARM processors. 

• Introduction to ARM processor architecture and pipelining
• RealView Development Suite (RVDS)
• ARM1176 processor
• ARM and Thumb instruction sets
• Exception handling
• ARM processor integration
• Hands-on use of development systems
• AMBA AHB, AXI and APB Protocol
• ARM1176 Memory Subsystem
• ARM1176 Memory Management
• ARMv6 Memory Types
• ARM1176 L1 and L2 Memory interface
• ARM1176 L2 Caches
• PrimeCell VIC interrupt controller
• ARM1136/1176 Interrupts
• Introduction to TrustZone
• Introduction to IEM
• ARM1176 clocks, resets and power management
• ARM1176 initialisation and bootstrap
• ARM processor simulation models
• ARM11 embedded core debug
• ARM1176 integration

All participants must be computer literate and have a basic understanding of the C programming language and a hardware description language such as VHDL or Verilog. An in-depth knowledge of microprocessors is not essential, but would be advantageous. 

This class uses training materials developed by ARM®. In addition, Doulos has developed dedicated workbooks for delegates who wish to use MDK, rather than RVDS, in the workshops. 

The ARM Architecture

ARM architecture • Overview of ARM • ARM based applications • ARM instruction set overview • ARM programmer's model • supporting technologies 

ARM Processor Core

ARM7TDMI and ARM9TDMI processor pipelines • ARM7 processor family • ARM9 processor family • ARM10E processor family • ARM11 processor family • StrongARM and XScale • Datapaths and instruction decoding 

Real View Developer Suite (RVDS) Overview

Compilers • Assembler • Linker • Codewarrior • Debuggers 

Real View Introductory Workbook

Practical work using RVDS 

Exception Handling

Overview of how to handle the different exceptions of an ARM core. Includes detailed examples. 

ARM1176 CPU Architectures

ARM7TDMI and ARM9TDMI processor pipelines • ARM7 processor family • ARM9 processor family • ARM10E processor family • ARM11 processor family • StrongARM and XScale • Datapaths and instruction decoding 

AMBA 3 Interface

Detailed description of the new AMBA 3 interconnect methodology • AXI, AHB and APB interconnect standards • PL300 bus matrix IP 

ARM1176 L1 Interface

Introduction to the Level1 Sub-System • System Control Coprocessor (CP15) features • Cache organisation • Tightly Coupled Memory (TCM) • DMA Interface • Cache timing • Write buffer 

ARM1176 L2 Interface

Introduction to the Level2 interface and memory system • Clock domains • L2 interface clocking, cache line fills • Non-cacheable fetches • Data interface • Peripheral interface • DMA interface 

ARM1176 L2 Caches

Inner and outer caches • Caching policies • TEX Remap • Communicating cache policy • Example system with L2 cache 

ARM Processor Simulation Models

The different ARM models and their use in the SoC design process • The new ARM RealView SoC Designer (SystemC based) design tool 

ARM1136/76 Interrupts

An overview of the ARM11 interrupt features, the factors contributing to low interrupt latency and an understanding of the ARMv6 re-startable instructions 

Introduction to TrustZone

Introduction to ARM TrustZone technology and its features• The new ARM secure mode and its functionality 

Introduction to IEM

Principles of the Intelligent Energy Manager (IEM) • Understanding the IEM software and its functions 

ARM1176 Clocks, Resets and Power Management

Overview of clock and reset behaviour and requirements • The different power management modes 

ARM1176 Memory Management

Introduction to the ARMv6 memory system • Caching policy and ARM1176 memory management 

ARM1176 Booting

Necessary steps for booting an ARM1176 processor •Sample bootstrap code. 

ARM11 Embedded Core Debug

Integrated debug features of the ARM11 processor family 

ARM1176 Integration

Key system design considerations • Summary of steps for the integration of an ARM1176 processor