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NEW SYSTEMVERILOG AND UVM FLEXIBLE TRAINING

In association with the Doulos Certified Training Partner in India - Test & Verification Solutions - we are pleased to announce a unique flexible training program available in Bangalore:

Courses available: SystemVerilog Flexible Training and UVM Flexible Training

Course features:

  • These flexible courses are self-paced training programs based on Doulos online training materials which are accessible on-demand for the duration of the training.
  • Location: Online on-demand during week days. T&VS Bangalore office (for Saturday lab sessions)
  • Duration:
    • Fast Track Course: 4 weeks (approx 4 hours per day, 5 days per week)
    • Slow Track Course: 8 weeks (approx 2 hours per day, 5 days per week)
  • Delegates also have access to :
    • Expert tutor support (by email) to answer queries and provide support for the labs.
    • Saturday workshops at the end of each week for both the Fast Track and Slow Track located the T&VS Bangalore Offices including:
      • 6 hours of assisted Face-to-Face labs - for the Doulos practical online labs
      • 2 hours of lab sessions with T&VS VIP and test benches.
    • online access to EDA playground - an online portal for running labs and having group discussions.
  • Delegates will receive a "Certificate of Completion" at the end of the training


Interested? Email your contact details to Doulos today and we will call you back
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Best-in-Class Training

For over 25 years, Doulos has set the global standard for high quality, independent technical training in hardware design and verification, embedded software and system design.

Offered in cooperation with verification specialists Test and Verification Solutions India Pvt Ltd, the courses on offer deliver project ready skills and expert knowhow in SystemVerilog/UVM, VHDL, the latest Arm Cores, and system level modelling using SystemC and TLM-2.0.

 

Upcoming Live Webinars

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Working with Devicetrees

Friday August 08 2025

1 hour session (All Time Zones)

This webinar will demystify how hardware is described by the devicetree and how the Linux kernel can use the data provided by the devicetree description to configure how device drivers talk to the underlying hardware.

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Python Magic Methods

Wednesday August 13 2025

1 hour session (All Time Zones)

This webinar will enable you to sharpen up your Python coding skills as we explore Python magic methods.

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Embedded C++: Dispelling Myths and Pre-conceptions

Friday August 15 2025

1 hour session (All Time Zones)

This webinar aims to resolve any fears you may have of using C++ for embedded applications, by exploring what actually goes on within the compiler…

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Understanding Random Stability in SystemVerilog and UVM

Wednesday August 20 2025

1 hour session (All Time Zones)

This webinar will explain random stability in SystemVerilog and in UVM, the Universal Verification Methodology.

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How to Accelerate Both your FPGA Application and Productivity

Friday August 22 2025

1 hour session (All Time Zones)

This webinar introduces the Vitis-based design methodology that offers a structured approach for all aspects of software development, debug and deployment for individual kernels and complete systems.

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