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The Designer’s Guide to Verilog

The Verilog HDL is an IEEE standard hardware description language. It is widely used in the design of digital integrated circuits.

Here we provide some useful background information and a tutorial, which explains the basics of Verilog from a hardware designer's perspective. We also provide some useful tips and pointers to other Verilog information on the web site.

Upcoming Live Webinars

Connecting AI to IoT Applications

Wednesday June 11 2025

1 hour session (All Time Zones)

This webinar will examine the application of AI in Edge / IoT situations. Although it uses an example for an industrial application, it will be of interest to anyone considering the use of AI technology for constrained devices.

Zephyr Insights: Scheduling and Threads

Wednesday June 18 2025

1 hour session (All Time Zones)

This webinar delves into the services offered by Zephyr to ensure real-time behaviour, with a primary focus on threads, priority management, and scheduling, highlighting similarities and differences to other RTOSs.

Developments in Accelerated Adaptable Technology

Friday June 20 2025

1 hour session (All Time Zones)

In this webinar you will learn about the core concepts behind the new Adaptable Compute Acceleration Platforms from AMD.

Formal Verification for Non-Specialists

Wednesday June 25 2025

1 hour session (All Time Zones)

This webinar explores the strengths and weaknesses of formal verification and what you need to know to use formal effectively without acquiring deep knowledge of how it works under-the-hood.

Introduction to Android Automotive

Friday July 18 2025

1 hour session (All Time Zones)

This webinar provides a valuable insight into the Android Automotive OS that runs "In Vehicle Infotainment" systems.