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The Designer’s Guide to Verilog

The Verilog HDL is an IEEE standard hardware description language. It is widely used in the design of digital integrated circuits.

Here we provide some useful background information and a tutorial, which explains the basics of Verilog from a hardware designer's perspective. We also provide some useful tips and pointers to other Verilog information on the web site.

Upcoming Live Webinars

Clock Domain Crossing

Wednesday July 16 2025

1 hour session (All Time Zones)

This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.

Introduction to Android Automotive

Friday July 18 2025

1 hour session (All Time Zones)

This webinar provides a valuable insight into the Android Automotive OS that runs "In Vehicle Infotainment" systems.

Understanding MPSoC Real-Time Processing

Wednesday July 23 2025

1 hour session (All Time Zones)

Explore the Arm® powered real-time processing capability of the UltraScale+ MPSoC and the hardware and software requirements for implementing time sensitive applications.

Getting Started with SystemVerilog Randomization

Friday July 25 2025

1 hour session (All Time Zones)

This webinar introduces the key concepts of randomization and constraints, including language constructs, the generation and constraint of data and randomization features and configuration approaches.

Python - Everything is an Object

Wednesday July 30 2025

1 hour session (All Time Zones)

This webinar will show you how all parts of Python have a lot in common, to help you adjust any mental map that you acquired from other languages and improve your Python programming skills.