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The Designer’s Guide to Verilog

The Verilog HDL is an IEEE standard hardware description language. It is widely used in the design of digital integrated circuits.

Here we provide some useful background information and a tutorial, which explains the basics of Verilog from a hardware designer's perspective. We also provide some useful tips and pointers to other Verilog information on the web site.

Upcoming Live Webinars

Working with Devicetrees

Friday August 08 2025

1 hour session (All Time Zones)

This webinar will demystify how hardware is described by the devicetree and how the Linux kernel can use the data provided by the devicetree description to configure how device drivers talk to the underlying hardware.

Python Magic Methods

Wednesday August 13 2025

1 hour session (All Time Zones)

This webinar will enable you to sharpen up your Python coding skills as we explore Python magic methods.

Embedded C++: Dispelling Myths and Pre-conceptions

Friday August 15 2025

1 hour session (All Time Zones)

This webinar aims to resolve any fears you may have of using C++ for embedded applications, by exploring what actually goes on within the compiler…

Understanding Random Stability in SystemVerilog and UVM

Wednesday August 20 2025

1 hour session (All Time Zones)

This webinar will explain random stability in SystemVerilog and in UVM, the Universal Verification Methodology.

How to Accelerate Both your FPGA Application and Productivity

Friday August 22 2025

1 hour session (All Time Zones)

This webinar introduces the Vitis-based design methodology that offers a structured approach for all aspects of software development, debug and deployment for individual kernels and complete systems.