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The Verilog HDL is an IEEE standard hardware description language. It is widely used in the design of digital integrated circuits.
Here we provide some useful background information and a tutorial, which explains the basics of Verilog from a hardware designer's perspective. We also provide some useful tips and pointers to other Verilog information on the web site.
Friday February 14 2025
1 hour session (All Time Zones)
This webinar will look at the ways formal helps your design verification process, including complexity analysis, bounded reachability analysis, overconstraining the design, setting cut points, and creating abstractions.
Friday February 28 2025
1 hour session (All Time Zones)
This webinar will explore ideas on identifying and deploying trained AI models on FPGAs and look at contemporary software tools and APIs which help in putting together an FPGA-based Edge AI solution.