Global training solutions for engineers creating the world's electronics
Menu

Find a Training Course

The Designer’s Guide to Verilog

The Verilog HDL is an IEEE standard hardware description language. It is widely used in the design of digital integrated circuits.

Here we provide some useful background information and a tutorial, which explains the basics of Verilog from a hardware designer's perspective. We also provide some useful tips and pointers to other Verilog information on the web site.

Upcoming Live Webinars

Image 1

Getting Started with UVM

Wednesday October 16 2024

1 hour session (All Time Zones)

This webinar will introduce you to the Universal Verification Methodology. The aim is to provide you with a base to start learning the rest of UVM, starting at why you would want to use it and the key components of a UVM test bench.

Register Now

Image 1

Deep Learning with FPGAs

Friday October 18 2024

1 hour session (All Time Zones)

This webinar examines Deep Learning with particular emphasis on the use of FPGAs as inference engines for convolutional neural networks.

Register Now

Image 1

C/C++ Memory Management: Heap Memory

Wednesday October 30 2024

1 hour session (All Time Zones)

This webinar explores the key features of C++ and shows where they provide useful advantages over traditional C approaches while producing code with comparable size and performance.

Register Now

Image 1

Clock Domain Crossing

Wednesday November 06 2024

1 hour session (All Time Zones)

This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.

Register Now