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Xilinx - Vivado HLS ONLINE Jetzt Auf Deutsch

Auch bekannt als C-based Design: High-Level Synthesis with Vivado HLS by Xilinx. Früher AutoESL. Doulos Live Online training

Bitte beachten Sie: Hier handelt es sich um ein ONLINE-Training mit LIVE Dozent.

Es behandelt bei ähnlichem Lernerfolg den selben Inhalt wie ein klassisches Training.

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Scheduled Course Dates: German Language

Scheduled Course Dates: English Language

Course Dates:
September 30th, 2019	ONLINE EurAsia	Enquire
October 21st, 2019	ONLINE Americas	Enquire
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Upcoming Live Webinars

The Rust Journey: Exploring Safe Systems Programming

Friday March 21 2025

1 hour session (All Time Zones)

In this webinar, we'll delve into the features and benefits of Rust: an evolutionary language that provides memory safety guarantees, performance and concurrency.

Accelerating Formal Verification Using Non-Determinism

Wednesday March 26 2025

1 hour session (All Time Zones)

This webinar will explain what non-determinism is, how it's used, and show lots of examples so you can take advantage of non-determinism to accelerate the verification of your designs.

A Guide to Productivity in Vivado using SystemVerilog

Friday March 28 2025

1 hour session (All Time Zones)

We will explore the features of SystemVerilog that are useful for RTL synthesis using the Vivado™ Design Suite from AMD, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.

EDA Playground Live! SystemVerilog Static and Automatic Lifetimes

Wednesday April 02 2025

30-minute session (All Time Zones)

This webinar presents SystemVerilog's constructs for managing static and automatic lifetimes of variables - demonstrated on EDA Playground.

Getting Started with Embedded Linux Security

Wednesday April 16 2025

1 hour session (All Time Zones)

This webinar will examine some of the main features and tools which can be used to make your embedded Linux system more secure.

Getting Started with UVM

Wednesday April 30 2025

1 hour session (All Time Zones)

This webinar will introduce you to the Universal Verification Methodology. The aim is to provide you with a base to start learning the rest of UVM, starting at why you would want to use it and the key components of a UVM test bench.