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1 hour session (All Time Zones)
Presenter: Dr Rahul Dubey
Time: 10-11am (BST) 11am-12pm (CEST) 2.30-3.30pm (IST)
Time: 10-11am (PDT) 11am-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)
Although SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to FPGA hardware designers. We explore the features of SystemVerilog that are useful for RTL synthesis using the Vivado™ Design Suite from AMD, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.
We start from the basic principles of RTL coding style in SystemVerilog, then focus on the language features that allow FPGA hardware designers to work very efficiently while at the same time avoiding synthesis pitfalls.
Content Summary:
Dr Rahul Dubey - Doulos Member Technical Staff, will be presenting this training webinar, which will consist of a one-hour session and will be interactive with Q&A participation from attendees.
Attendance is free of charge
If you have any queries, please contact webinars@doulos.com
Visit www.doulos.com/knowhow
Please contact Doulos to schedule a public course to suit you, or to discuss onsite training.
