Settings Generics/Parameters for Synthesis

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Settings Generics/Parameters for Synthesis

VHDL has the powerful feature of generics, while Verilog has the option of defining parameters. Both these techniques allow parameterisable designs, that is designs that can be easily re-used in different situations. Here, the testbench wires up the entity declaration of a parameterised counter in VHDL:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Counter is
  generic (NBits, MaxCount : positive);
  port ( Reset, Clock, UpDn : std_logic;
         Q                  : std_logic_vector(NBits-1 downto 0));
end entity Counter;

This can be simulated - the testbench wires up the ports and sets the generic as follows

  U1: entity work.Counter
     generic map (NBits => 8, MaxCount => 100)
     port map (Reset => Reset, Clock => Clock,
               UpDn => UpDn, Q => Q);

This works fine for simulation, but of course if you try to synthesize the counter on its own, the synthesis tool does not know the value of the generics. One way round this is simply to give the generics default values - the synthesis tool will then use those defaults. If you do that, it makes sense to re-write the generic declaration so that each generic can be given a different default value, i.e:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity Counter is
  generic (NBits : positive := 8;
           MaxCount : positive := 255);
  port ( Reset, Clock, UpDn : std_logic;
         Q                  : std_logic_vector(NBits-1 downto 0));
end entity Counter;

To go further than this, and override the generics from a synthesis tool, you'll have use tool specific features. The rest of this page shows some examples. Note that because each tool has to analyze the code first to identify the generics, it is a good plan to put default values as shown above so that the code will definitely synthesize even without overriding the generic values.

Setting Generics/Parameters in Altera Quartus II

Load in your design, and analyze it by clicking the button Start Analysis and Synthesis.

Now use the menu option Assignments > Settings... and click on Default Parameters. You can now set the generics - see the following screen shot:

Of course you can also use Tcl.

  set_parameter -name NBits 4
  set_parameter -name MaxCount 9

Setting Generics/Parameters in Lattice ispLever Classic

Lattice ispLever Classic uses Synopsys Synplify Pro® as its synthesis tool, so see the section below about Synopsys Synplify Pro®.

Setting Generics/Parameters in Lattice Diamond

In Lattice Diamond, set up your project, import your code, and synthesise it using either Lattice Synthesis Engine (LSE) or Synopsys Synplify Pro®. To add VHDL generics or Verilog compiler directives and parameters, carry out the following steps:

In the File List view, right-click the implementation name and choose Properties. The Project Properties dialog box opens showing the implementation properties.
In the HDL Parameters row, click under Value.
Type the statements as a single text line with different statements separated by semi-colons (;).
When done, click OK.

Here is a screenshot.

Setting Generics/Parameters in Mentor Precision RTL

Mentor Precision RTL can set generics, but it must be done from a Tcl command. The Tcl command has to set a "list of lists" as follows:

setup_design -overrides { {NBits 4} {Depth 16} }

Note the use of curly brackets to enclose each list. This command can be typed at the console of the Precision GUI, or put in a Tcl script.

Setting Generics/Parameters in Microsemi Libero

Microsemi Libero uses Synopsys Synplify Pro® as its synthesis tool, so see the section below about Synopsys Synplify Pro®

Setting Generics/Parameters in Synopsys Synplify Pro®

Synplify can set generics from the menu Options > Configure VHDL Compiler > VHDL tab. This menu has an Extract Generic Constants button which will identify the generics and add them to the form, so you can fill in the values. Here is a screenshot.

Alternatively with the magic of Tcl:

set_option -hdl_param -set nbits 4
set_option -hdl_param -set maxcount 9

Setting Generics/Parameters in Xilinx ISE

In Xilinx ISE, set up your project, import your code, and synthesise it. To set generics, you'll need to make sure that you are viewing Advanced properties in the synthesis properties.

To do this, carry out the following steps:

Make sure Design View is set to Implementation
Highlight your design in the Hierarchy window
In the Processes window, right-click on Synthesize - XST and select Process Properties
Highlight the Synthesis Options category in the left of the form
Set the Properties Display Level to Advanced

Now you will be able to type in your generic/parameter settings - see the following screenshot.

The syntax is a space separate list of assignments such as NBits=4 MaxCount=9.

In Xilinx ISE Tcl, the following command has been created:

project set "Generics, Parameters" "NBits=4 MaxCount=9" -process "Synthesize - XST"

Setting Generics/Parameters in Xilinx Vivado

In Xilinx Vivado, set up your project, import your code, and synthesise it. To set generics, carry out the following steps:

Select Project Settings from the Project Manager section of the Flow Navigator window.
Highlight the General option in the left of the Project Settings dialog box.
Select the button to the right of the Generics/Parameters field.
Select the + button in the Generics/Parameters dialog box.

Now you will be able to type in your generic/parameter settings - see the following screenshot.

In Xilinx Vivado Tcl, the following command will synthesise a design using Vivado Synthesis with the specified generics/parameters and values (plus any additional synthesis options).

synth_design -generic NBits=4 -generic MaxCount=9 ...

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