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VHDL Testbench Creation Using Perl

Hardware engineers using VHDL often need to test RTL code using a testbench. Given an entity declaration writing a testbench skeleton is a standard text manipulation procedure. Each one may take five to ten minutes.

Every design unit in a project needs a testbench. Generating testbench skeletons automatically can save hours per project. However, a little Perl programming can reduce that time to seconds in future.


Our web server is set up to run Perl scripts. We've written a Perl script to generate a skeleton testbench given an entity declaration. In fact, if an architecture is supplied then the Perl script will add in a Reset and Clock generator process (if the architecture uses a clock). Configuration declaration(s) are generated too.

Copy and paste your own declarations or use our sample code below. Then click the Generate VHDL Testbench button.



Great training!! Excellent Instructor, Excellent facility ...Met all my expectations.
Henry Hastings
Lockheed Martin

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