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Practical Asynchronous SystemVerilog Assertions
by Senior Member Technical Staff, Doug Smith
Nearly all digital designs have asynchronous behaviors. For example, designs often have asynchronous resets or asynchronous inputs like interrupts or ready signals. Some RTL designs are inherently asynchronous in nature as in the case of power management modules receiving off-chip boot up signals. Asynchronous behaviors also appear in the form of asynchronous handshaking protocols for peripheral devices or in the case of synchronizers between clock domain crossings.
SystemVerilog assertions (SVA) provide a great way of testing and describing design behaviors. However, using SVA to capture asynchronous behavior is not always straightforward due to the scheduling semantics of SystemVerilog. While triggering on an asynchronous event is easy enough, the sampling of the assertion inputs is either dependent on its context as in the case of immediate assertions or synchronous by nature as in the case of concurrent assertions. Often, asynchronous events occur before the design has updated its state, requiring the checking of the RTL to be delayed. Further, the timing of asynchronous events may be hard to predict, making it harder to describe using an assertion.
In this paper, eight common asynchronous scenarios are presented and SVA solutions for checking them. In addition, an alternative approach using a global fast clock is presented as both a portable simulation solution and something that works for both formal verification and emulation. Lastly, incorporating functional coverage into the asynchronous checking is also discussed.
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Example Code
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