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What is the difference between Verilog and VHDL?
On the surface, not that much. Both are IEEE standards and are supported by all the major EDA vendors. Both can be used for designing ASICs and simulating systems. However, VHDL is altogether a grander language. Its support for system level modeling and simulation is far more comprehensive than Verilog, despite some Verilog built-in functions for stochastic modeling. However, VHDL requires longer to learn and is not so amenable to quick coding. As a final thought many engineers need to know both languages due to the use of IP (Intellectual Property) blocks written in "the other" language.
What versions of Verilog are there?
The original Verilog was standardised by the IEEE as Verilog 95; there were then improved version releases, Verilog 2001 and 2005, before it was merged into the SystemVerilog standard. If you want to know more about SystemVerilog, have a look at our 5 day Comprehensive SystemVerilog.
Can I use Verilog for the analog part of a design?
No. You can't design analog circuitry in Verilog, however you can model analogue circuitry in Verilog (said this digital designer!). In theory, Verilog can be used to model the behaviour of any system or component. However, Verilog does not offer the same level of modeling accuracy as say Spice, without an awful lot of work.
How must I write Verilog to make it synthesisable?
Writing Verilog for synthesis is not particularly difficult, but you need to be disciplined, not only in your use of Verilog syntax but also your approach to writing Verilog for synthesis. It is this latter aspect which many engineers overlook; thorough training is really the only way to avoid making poor strategy decisions in writing synthesisable Verilog.
A Verilog design can be moved to any tool or technology. Right?
On the face of it, this is true. Verilog was designed to be and is a technology independent design language. However, there is less of a compliance issue between different simulators than there is for synthesis tools. Generally speaking, moving Verilog code from one simulator to another involves one or two minor changes to the Verilog, assuming you don't use a lot of system tasks (which tend to be proprietary) in your code. Two different synthesis tools may support two quite different Verilog subsets. This is particularly an issue for us at Doulos in developing our training courses, because we like to present a reasonably generic approach to writing Verilog for synthesis. This means that the Verilog we teach you is guaranteed to be more transportable between synthesis tools than it otherwise would be. Our pain is your gain! In addition because we are so aware of the differences between synthesis tools, this means that we emphasise the best way of writing Verilog to get the best from your synthesis tool.
I can see how to write abstract behavioural descriptions in Verilog, but how do you describe and simulate the actual hardware?
This is probably the biggest hurdle that many hardware engineers face when moving to Verilog. After all, sometimes we need to be able to describe actual implementation as well as abstract functionality. The way to describe "physical" hardware in Verilog is to write Verilog models of those components. This is supported in Verilog through the use of instantiation. Verilog does not allow you to physically simulate your hardware. You can only simulate a model of that component in a Verilog simulation.
What is Synthesis?
Synthesis is the stage in the design flow which is concerned with translating your Verilog code into gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor.
How about on-line information resources?
You're already here! Try the Verilog section of our High Level Design Library for examples of Verilog models and assorted tips and tricks. In addition, check out the comp.lang.verilog newsgroup.
