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This model shows how the others expression can be used in modeling a common hardware function, namely a demultiplexer.
The demux_32 code relies on the use of a conversion function in order to minimize the amount of VHDL code that needs to be written; to_integer is defined in the numeric_std package which is compiled into the ieee library.
Notice also that the y output is initialized to all '0' at the start of the process, so even though there is no else branch for the if statement, incomplete assignment does not apply (and therefore you will not get latches from synthesizing this code).
You are welcome to use the source code we provide but you must keep the copyright notice with the code (see the Notices page for details).
-- demux_32
--
-- +-----------------------------+
-- | Copyright 1997-2008 DOULOS |
-- +-----------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity demux_32 is
port (
a : in std_logic_vector(4 downto 0);
enable : in std_logic;
y : out std_logic_vector(31 downto 0)
);
end demux_32;
architecture behaviour of demux_32 is
begin
demux_a_to_y: process (a, enable)
begin
y <= (others => '0');
if enable = '1' then
y(to_integer(unsigned(a))) <= '1';
end if;
end process;
end behaviour;
To download the VHDL source code for this model, click here.