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VHDL-2008: Major Enhancements

The majority of changes to VHDL that VHDL-2008 introduces are useful and important, but relatively minor. However, the following represent major enhancements to the language.

PSL is integrated into VHDL

VHDL already includes the assert statement, which is used for adding simple checkers to VHDL models. You assert that an expression evaluates to TRUE, meaning that you expect that this will be the case whenever the assertion is evaluated. If the expression is in fact FALSE the simulator writes out an error message.


PSL (Property Specification Language) extends this idea by providing a syntax for describing the expected behaviour of a circuit over time and for checking that the VHDL code implements that behaviour. Until now, PSL statements could only be added to VHDL models as meta-comments (“comments” that a compiler may in fact interpret as extended syntax) or in separate files (vunits). For example:
--psl assert always req -> next[2] (grant);
VHDL-2008 now includes the simple subset of PSL as part of the standard VHDL syntax. All PSL keywords are now reserved in VHDL. (Using PSL’s simple subset means using PSL in a way that simulators can handle.) In VHDL-2008, the example given above can be written as a concurrent statement like this:
assert always req -> next[2] (grant);
Similarly, PSL declarations – for example, of clocks, properties and sequences – may be included in VHDL declarative regions.


If a concurrent statement could be interpreted either as a VHDL assert statement or a PSL directive, the VHDL interpretation is used:
assert not (a and b);
is interpreted as VHDL, not PSL.


Some PSL keywords are now reserved keywords in VHDL. For example, property, and sequence.


Other PSL keywords only have a special meaning within PSL declarations and directives. For example, before is a keyword in PSL, but not in VHDL.


To learn more about PSL, see The Designer's Guide to PSL.

Package and subprogram generics.

In VHDL, generics have always been allowed on entities. This enables you to write parameterized design entities, such as an N-bit counter. VHDL-2008 allows generics on packages and subprograms too. This makes it more convenient to write flexible, re-usable code. For an example, see the synthesizable fixed and floating point packages below.

Generic types, subprograms and packages.

In VHDL generics are constants. In VHDL-2008 they may also be types, subprograms or packages.
Here is an entity that has a type generic (data_type) and a subprogram generic (function increment). We can’t use the "+" operator in the architecture, because "+" is not supported for arbitrary data types.
library ieee;
use ieee.std_logic_1164.all;
entity incrementer is
  generic (type data_type;
           function increment (x: data_type) return data_type);
  port (I : in data_type;
        O : out data_type;
        inc : in std_logic);
end entity incrementer;
architecture RTL of incrementer is
  O <= increment(I) when inc = '1';
end architecture RTL;
This shows how we might instance this entity:
incr_inst : entity work.incrementer
  generic map ( data_type => std_logic_vector(7 downto 0),
                increment => add_one )
  port map ( I => I, O => O, inc => ena );

New synthesizable fixed and floating point arithmetic packages.

One application of these extended generics is found with the new fixed and floating point arithmetic packages that are part of VHDL-2008.


Here is part of the declaration of fixed_generic_pkg:
package fixed_generic_pkg is
  generic (fixed_round_style    : fixed_round_style_type   := fixed_round;
           fixed_overflow_style : fixed_overflow_style_type := fixed_saturate;
  -- ...
and here is part of the declaration of fixed_pkg :
package fixed_pkg is new IEEE.fixed_generic_pkg
  generic map (
    fixed_round_style         => IEEE.fixed_float_types.fixed_round,
    fixed_overflow_style_type => -- ...
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