This page summarises a number of other changes, most of which are quite small. Some of these have already been mentioned in passing on other pages, and are summarised here as well. These changes include:
Below you'll find some more detail about the following changes:
VHDL-2008 defines two new functions minimum and maximum. These are defined for scalar or array types.
minimum(10,11) -- returns 10 -- bv1 contains "0111" bv2 contains "1000" maximum(bv1, bv2) -- returns "1000"
Note that comparison of vectors is not done numerically unless you include an arithmetic package - the arithmetic packages overload the above functions to operate arithmetically.
Before VHDL-2008, the strength reduction functions were not defined consistently on signed, unsigned, and std_(u)logic_vector. In VHDL-2008 the following functions are now consistently defined on these types:
is_X to_X01 to_X01Z to_UX01 to_01
One of the main changes to composite types (array and record types) is that now you can use unconstrained array and record elements. For instance the following declarations are now legal:
type myArrayT is array (natural range <>) of std_logic_vector; type myRecordT is record a : std_logic_vector; b : std_logic_vector; end record;
The language has also been extended to allow declaration of fully or partially constrained objects and types. For instance the above record type may be used to declare a fully constrained variable as follows:
variable R : myRecordT( a(7 downto 0), b(15 downto 0) );
In certain contexts (for instance when using unconstrained ports or procedure parameters) it is possible to use the keyword open to represent a dimension that should remain unconstrained.
VHDL-2008 adds a number of new predefined array types as follows:
type boolean_vector is array (natural range <>) of boolean type integer_vector is array (natural range <>) of integer type real_vector is array (natural range <>) of real type time_vector is array (natural range <>) of time
There is a new version of case which allows don't care behaviour, case?. Here is an example:
case? sel is when "1---" => o <= "11"; when "01--" => o <= "10"; when "001-" => o <= "01"; when "0001" => o <= "00"; when others => null; end case;
The comparison is carried out using the matching equality operator ?= which means that the don't care character '-' is truly treated as don't care, and also that (for instance) 'H' matches '1'. As for a regular case statement, each value of the expression at the top must be represented exactly once amongst the set of choices: when using pattern matching, you have to be careful that patterns that include the '-' do not overlap.
For verification, it is sometimes convenient to be able to "override" the value of a signal. This can be used for error injection, for instance. Of course this is always possible using vendor-specific commands, typically written in Tcl. But VHDL-2008 allows this in pure VHDL.
It is also possible to remove the overridden value using the release keyword.
Finally it is possible to make a distinction between the effective and driving value of a signal (there are restrictions on ports depending on their mode).
<< tb.uut.s >> <= force '1'; -- inject error << tb.uut.s >> <= release; -- stop overriding v <= force in '1'; -- force effective value v <= force out '0'; -- force driving value v <= release in; -- release effective value v <= release out; -- release driving value
With VHDL-2008 it is now possible to achieve the same confusing errors you can with a language like C, and comment out a big chunk of code by accident, with a delimited (block) comment. (Can you tell I'm not a big fan?)
/* s <= 1; r <= 2; */
Both 'INSTANCE_NAME and 'PATH_NAME have been corrected so that they cope with shared variables of protected type (introduced in VHDL 2000), and overloaded operators. Previously the paths and instance strings produced by these attributes did not include operator names and shared variables.
An additional environment package is added. This package allows VHDL code to control the simulator, and to find out the simulator time resolution. The package is std.env.
procedure stop(status:integer); prodedure stop; procedure finish(status:integer); procedure finish; function resolution_limit return delay_length;
stop causes a simulation to stop but not to quit. finish causes a simulation to quit. The resolution_limit function allows the user to find out the simulator resolution limit - for instance you could wait for a minimum time step using
wait for env.resolution_limit;
VHDL-2008 has a means of specifying that a block of data is encrypted. This uses an additional feature - the tool directive. Tool directives are arbitrary words preceded by a backtick character `. The idea of tool directives is that they are interpreted by tools, they don't have any meaning to a VHDL compiler.
For IP encryption, a set of predefined tool directives is defined as follows:
`protect begin `protect end `protect begin_protected `protect end_protected `protect author `protect author_info `protect encrypt_agent `protect encrypt_agent_info `protect key_keyowner `protect key_keyname `protect key_method `protect key_block `protect data_keyowner `protect data_keyname `portect data_method `protect data_block `protect digest_keyowner `protect digest_keyname `protect digest_key_method `protect digest_method `protect digest_block `protect encoding `protect viewport `protect decrypt_license `protect runtime_license `protect comment
Many of these tool directives have additional parameter values.
Here's a short example of what some VHDL code might look like using IP encryption:
entity e is -- ports omitted end entity; architecture RTL of e is `protect data_keyowner = "Doulos User" `protect data_keyname = "Doulos Key" `protect data_method = "rsa" `protect encoding = (enctype= "quoted-printable") `protect begin -- code omitted begin -- code omitted `protect end end architecture RTL;