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VHDL-2008 includes standards that were in the past separate. These standards were only separate from the main VHDL standard because they were developed after VHDL itself. This led to some "quirks"; for instance the std_match function which does a "don't care" comparison between std_logic_vectors was defined in the numeric_std package - even though none of the other functions and operators in numeric_std work on type std_logic_vector!
Extra features have been added to the standard packages.
While some of these standards are packages, VHDL-2008 also incorporates PSL and the VHDL Programming Interface (VHPI). PSL is discussed here.
The VHDL Programming Interface 1076-2007c is a relatively new standard which defines a C interface to VHDL. The standard is complex and allows manipulation of the simulation process, static data, and dynamic data. From the point of view of VHDL-2008 all we need to know is that it is now included in VHDL!
The original VHDL definition included only the types defined in the package std.standard. Over the years the following packages have been developed to work with VHDL:
All these packages are now incorporated into the main VHDL standard.
In addition a number of packages have become very widely used even though they are not official standards. These are:
As mentioned previously The replacements for std_logic_unsigned and std_logic_signed are the new packages numeric_std_unsigned and numeric_std_signed.
The functionality of the std_logic_textio is now included in IEEE.std_logic_1164. The user may still include std_logic_textio, but the package is now just a "stub" - the functions are actually provided in IEEE.std_logic_1164.
Not only is std_logic_1164 incorporated into VHDL-2008, it has been improved. The main changes are
Here are some examples of the new operators:
signal o : std_logic;
signal x,y,v : std_logic_vector(2 downto 0);
o <= i1 when ?? sel else i2; -- intepret sel as boolean
o <= and v; -- reduction operator, returns std_ulogic
o <= x ?= y; -- ?= and ?/= work on std_(u)logic_vector
-- ?= ?/= ?< ?<= ?> ?>= on std_(u)logic
The matching operators return the appropriate operand type, rather than boolean.
Of course textio has been part of VHDL since the original standard in 1987, so perhaps does not really belong in this section. However it has been extended in a way that incorporates features sometimes provided by other non-standard packages (for instance the Mentor SDK). So this section summarises what is new.
VHDL-2008 includes additional functions to read and write std_logic and std_logic_vector (historically people used the non-standard std_logic_textio to provide these functions).
There is now a function swrite to simplify writing string literals. Here is an example:
write(L, string'("-- start of file")); -- type qualification required
swrite(L, "-- start of file"); -- no type qualification required
If you wanted to write text to both a file and to standard output, it was not easy to do in VHDL 2002 and earlier - the simplest solution was simply to call the writeline procedure twice, once for each destination. VHDL-2008 adds a procedure tee to do this for you:
tee(F, L); -- writes to file F *and* to standard output
If you want to explicitly flush a file without closing it, there is a procedure for that very purpose:
flush(F); -- flushes F to disk
The procedures formerly in std_logic_textio for hex and octal format writing are included in textio. In addition, there are overloaded implementations of to_string for many different data types. There is also a function called justify to format data without using the justification and field width parameters of the standard read and write functions. Here is a slightly contrived example showing some of these features:
write(L, justify(to_string(now,ns), field => 10) &
justify(to_hstring(sel) , field => 2 ) );
Note the introduction of to_hstring as well.
Now all these packages are available, it can be a bit tedious adding all the appropriate package context clauses in front of your testbench or design. VHDL-2008 provides a way of grouping a set of library and use statements into a named context. Once the context is declared, it can be used repeatedly.
For convenience there are some built-in contexts for common purposes such as writing synthesisable code.
Here's an example which you might declare contexts for a site and a project:
context site_context is -- compiled into library sitelib library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use sitelib.sitepack.all; end context; context proj1_context is -- compiled into library proj1lib library sitelib; context sitelib.site_context; use proj1lib.proj1pack.all; end context;
Now anyone on the proj1 project can just say
library proj1lib; context proj1lib.proj1_context;
and they have a project standard setup in two lines!
The VHDL-2008 standard defines two built-in contexts as follows:
context IEEE_BIT_CONTEXT is library IEEE; use IEEE.numeric_bit.all; ene context IEEE_BIT_CONTEXT; context IEEE_STD_CONTEXT is library IEEE; use IEEE.std_logic_1164.all; use IEEE.Numeric_Std.all; end context IEEE_STD_CONTEXT;