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VHDL Vector Arithmetic using Numeric_std

First a little bit of history... When VHDL came out in 1987, there were a couple of missing features. Firstly, there was no built-in multi-value logic type - the only logic types available were bit and boolean, both of which only had two values. Initially, each synthesis tool vendor created its own multi-value logic package, which led to a lack of portability. That in turn led to "IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Stdlogic1164)", which defines the resolved multi-value logic type std_logic.

Std_logic became the standard logic type in VHDL design. The second missing feature was a standard way of doing arithmetic on vector types - bit_vector and std_logic_vector. Again synthesis vendors developed their own packages, some of which became very widely used; but then the IEEE created "IEEE 1076.3 Standard VHDL Synthesis Packages". This defines two packages, one for use with types based on bit (numeric_bit) and one for use with types based on std_logic (numeric_std).

We cover vector arithmetic extensively on our Comprehensive VHDL course, including two useful diagrams summarising the contents of numeric_std. These two diagrams are reproduced on this page for your reference. The first is a summary of the contents of numeric_std - the second is a diagram showing how to convert different data types.

The following diagram summarises the available operators and functions

and the second diagram summarises type conversions.

Great training!! Excellent Instructor, Excellent facility ...Met all my expectations.
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Lockheed Martin

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