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Signal Integrity PCB Vias and Remedies
30 minute session (All Time Zones)
Presenter: Lee Ritchey
Time: 10-11am (GMT) 11-12pm (CET) 3.30-4.30pm (IST)
Time: 10-11am (PST) 11-12pm (MST) 12-1pm (CST) 1-2pm (EST)
This webinar will explore the effects of routing vias and connector plated through holes on very high data rate signals using actual test results from as-built PCBs.
The Siemens Hyperlynx signal integrity tool will be used to examine a proposed signal path in an integrated circuit tester to determine whether the vias and plated through holes in the signal path will present a signal integrity problem.
The analysis will determine whether back drilling of the vias and plated through holes will be needed to ensure an acceptable signal to the IC being tested.
The webinar will conclude with measurements of the actual signals at the IC pins after the test PCBs were fabricated.
The broadcast presented by Lee Ritchey includes interactive Q&A available to attendees throughout.
Lee Ritchey is one of the industry´s premier authorities on high-speed PCB and system design. He has taught more than 10,000 engineers and designers throughout the world, including virtually all major suppliers of equipment to the Internet and the Cloud.
Attendance is free of charge
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