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Designing with the AMD Versal Adaptive SoC: Network on Chip ONLINE WORKSHOP

Standard Level - 2 sessions (4 hours per session including breaks)

With thanks to AMD for sponsoring this workshop:
It is available to attend FREE OF CHARGE (Usual price $990)

April 18-19 2024 - EurAsia - Register now »

April 18-19 2024 - Americas - Register now »

The Versal™ adaptive SoC from AMD is multi-featured, offering unprecedented system level performance and integration. 

This workshop (delivered in 2 half-day sessions) introduces the Versal adaptive SoC Network on Chip (NoC).

Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.

The workshop is designed to maximize individual engagement and learning.  Each attendee is encouraged to informally ask pertinent questions throughout, to actively participate in the learning process. 

Hardware developers and system architects, whether migrating from existing devices or starting out with the Versal adaptive SoC.

The workshop has been created to be accessible by a wide audience with standard technology requirements.

If you have not attended a Doulos workshop or webinar before, you can check your connection with the meeting service here »

Delivered across 2 half-day sessions 

  • Architecture Overview for Existing AMD Users
    Introduces to students that already have familiarity with AMD architectures to the new and updated features found in the Versal adaptive SoC devices. 
  • Versal adaptive SoCs compared to Zynq UltraScale+ Devices
    The Versal adaptive SoC has a number of similarities to the Zynq™ UltraScale+™ MPSoC devices. Understanding what is the same, what is different, and what is brand new helps put this powerful new part into context. 
  • NoC Introduction and Concepts
    Reviews the basic vocabulary and high level operations of the NoC. 
  • NoC Architecture
    Provides the first deep dive into the sub-blocks of the NoC and how they are used. Describes how the NoC is accessed from the programmable logic 
  • Design Tool Flow Overview
    Designers come to the Versal adaptive SoC devices with different goals. This module explores how traditional FPGA designers, embedded developers, and accelerated system designers would use the various tools available in the AMD toolbox. 
  • NoC DDR Memory Controller
    The integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC's DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use. 
  • NoC Performance Tuning
    Synthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance. 
  • System Design Migration
    Describes how different users will leverage tools and processes to migrate their designs to the Versal adaptive SoC devices. 


Please come prepared to actively participate and engage directly with the workshop facilitator.

This workshop is delivered in 2 half-day sessions of interactive training comprising presentations with Q&A.

  • Each session duration is up to 5 hours including breaks 
  • Start times:
    • Europe and Asia Time Zones:
      0830 BST | 0930 CEST | 1300 India (IST)
    • Americas Time Zones:
      0830 PDT | 1030 CDT | 1130 EDT
  • There are no specific hardware requirements for this training please check your connection with GoToWebinar if you have not used it to attend a Doulos event before.

The workshops have kindly been sponsored by AMD, and are available to attend FREE OF CHARGE.

Usual value of this training is $990 / €840 

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