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These one hour training sessions are presented by Subject Matter Specialists and include live interactive Q&A support from the Doulos team throughout.

Registration and attendance is completely FREE!

Understanding Random Stability in SystemVerilog and UVM

Wednesday, November 03, 2021

Time: 10-11am (GMT) 11-12pm (CET) 3.30-4.30pm (IST)
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Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)
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Webinar Overview:

A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs to be modified and is known in SystemVerilog as random stability.

In this webinar, we explain:

  • Random stability in SystemVerilog and in UVM, the Universal Verification Methodology
  • The pitfalls of poor random number generation and seeding
  • How to ensure that simulation results are reproducible in native SystemVerilog and in UVM through a careful presentation of hierarchical seeding, manual seeding, thread stability, and object stability
  • Exactly what changes you can and cannot make to UVM code without disturbing the random stimulus generation.

Examples written in the IEEE Std 1800™ SystemVerilog language and UVM 1.2 will be shown running on the Questa Advanced Simulator from Siemens.

This training webinar is presented by Doulos Senior Member Technical Staff, Matthew Taylor and will consist of a one-hour broadcast with interactive Q&A available to attendees throughout.

 

The Keys to SystemC & TLM-2.0:
How to be Successful

Friday, November 05, 2021

Time: 10-11am (GMT) 11-12pm (CET) 3.30-4.30pm (IST)
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Time: 10-11am (PDT) 11-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)
REGISTER NOW »

Webinar Overview:

SystemC has become well-established as the language of choice for system modeling and virtual platform creation and integration, and is now being applied successfully for high level synthesis. SystemC models also frequently appear as reference models in the hardware verification flow.

This session is aimed at hands-on hardware or software engineers who might know Verilog or C but have no previous experience of SystemC. It will explain what you need to know to be successful with SystemC by exploring some fundamental questions including:

  • What is SystemC and how is it used?
  • What does modern SystemC code look like?
  • What differentiates SystemC from SystemVerilog?
  • What use cases best fit SystemC?
  • What is TLM?
  • Where can I learn more?

The session will be presented by David C Black, Doulos Senior Member of Technical Staff and co-author of "SystemC: From the Ground Up". It will consist of a one-hour session, (see below for details) and will be interactive with Q&A participation from delegates.