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Spartan-6 Migration to 7 Series or UltraScale+ ONLINE WORKSHOP

Standard Level - 2 sessions (4 hours per session including breaks)

With thanks to AMD for sponsoring this workshop:
It is available to attend FREE OF CHARGE (Usual price $990) 

Please contact us for further details »

This free online workshop covers all the necessary  steps  to migrate a Spartan®-6 design made in ISE to the 7-Series or UltraScale™/UltraScale+ devices using the Vivado® ML tools.


It is also useful for engineers who want to refresh their knowledge of XDC timing constraints. 

In addition to Clock and IO constraints, multicycle path, false path and other timing exceptions constraints are also discussed.

  • Spartan-6 users who want to migrate their existing design to the latest FPGA technology and are new to Vivado ML.
  • FPGA designers who want to refresh their knowledge of XDC timing constraints. In addition to Clock and IO constraints, multicycle path, false path and other timing exceptions constraints are also discussed.

The workshop has been created to be accessible by a wide audience with standard technology requirements.

If you have not attended a Doulos workshop or webinar before, you can check your connection with the meeting service here »

  • Workshop Overview

    The emphasis of this workshop is on:

    • Comparing Spartan-6 with 7 Series Architectures
    • Migration flow
    • Introducing Vivado ML
    • Introducing the IP Flow
    • Creating XDC timing constraints

    Workshop Agenda

    • Introduction
    • Spartan-6 to Spartan-7 Architecture Migration 
      Guidance on migrating from Spartan-6 to other families – The architectural differences between the Spartan-6 and Spartan-7/Artix®-7 – Some available resources to help guide people through the transition from ISE to Vivado
    • Introduction to Vivado ML Editions Tool FLow
      Describes the various design flows in the Vivado Design Suite - Explains how the Vivado Tools flow is different from ISE tool flow - Identifies and describes the supported use models in the Vivado Design Suite - What is a Netlist - How to create a project in Vivado ML and explain the different flow options - Briefly talk about IP Integrator and Vitis HLS
    • Vivado ML Project Mode
      Describes the project mode use model in the Vivado ML – Describes the structure and files of a project – How to create a simple Vivado ML project in project mode
    • Synthesis and Implementation
      Describes the synthesis and implementation processes in the Vivado IDE and the reports that are available after the process
    • Vivado IP Flow
      Describes the Vivado IP Flow , how to access IP from the IP catalog and describe the output files and synthesis flow
    • Introduction to XDC Clock Constraints
      Provides a brief introduction to clock constraint and their properties in the Vivado Design Suite
    • Generated Clocks and Clock Groups
      Describes generated clocks in the Vivado ML Editions and introduces the application of clock group constraints that are used by the Vivado timing engine to resolve timing issues
    • IO Constraints and Virtual Clocks
      Introduces how I/O timing constraints are made with the Vivado IDE for single data rate applications
    • Setup and Hold Timing Analysis
      Covers the setup and hold timing analysis.
    • Timing Constraints Wizard
      Explains use of the Timing Constraints Wizard to create timing constraints and validate their completion 
    • UltraFast Design Methodology Design Creation
      Introduces the design creation guidelines for the UltraFast™ Design Methodology
    • Introduction to Timing Exceptions
      Introduces the application of multicycle paths, false paths, and max/min delay exception timing constraints
    • Timing Constraints Priority
      Discusses the XDC precedence for timing exception constraints priority.

This workshop is delivered in two 4 hour sessions of interactive training comprising presentations with Q&A.

  • Americas workshop start time 
    • February 23-24 2023:
      0830 PST | 1030 CST | 1130 EST
  • EurAsia workshop start time
    • February 23-24 2023:
      0830 GMT | 0930 CET | 1400 IST
  • There will be regular breaks throughout the training including one extended break 
  • There are no specific hardware requirements for this workshop, please check your connection with GoToWebinar here if you have not used it to attend a Doulos event before.

FREE OF CHARGE sponsored by AMD Xilinx

Please contact us for further details »

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