Standard Level - 2 sessions (4 hours per session)
With thanks to AMD for sponsoring this workshop:
It is available to attend FREE OF CHARGE (Usual price $990)
January 25-26 2024 - EurAsia - Register now »
January 25-26 2024 - Americas - Register now »
The Versal® Adaptive SoC from AMD is multi-featured, offering unprecedented system level performance and integration.
This informative workshop (delivered in 2 half day sessions) is a comprehensive and practical introduction to the features and capabilities.
We’ll first cover the broader Versal Adaptive SoC device. We’ll then focus on a practical example, optimizing a given application for the AI Engine resources.
The workshop is designed to maximize individual engagement and learning. Each attendee is encouraged to informally ask pertinent questions throughout, to actively participate in the learning process.
Software and hardware developers, system architects, and anyone who wants to learn about the Versal Adaptive SoC device from AMD Xilinx.
The workshop has been created to be accessible by a wide audience with standard technology requirements.
If you have not attended a Doulos workshop or webinar before, you can check your connection with the meeting service here »
Delivered across 2 half-day sessions
Versal Adaptive SoC: Structural Overview – Big picture overview, processing engines, connections and capabilities.
Intro to AI Engines – Scalar and vector processing unit, SIMD data-path, multi-kernel control and communication
PS Overview – Introduce the A72 and R5F processors, MPSoC migration, the role of the PMU, device boot, etc.
PL Fabric – The traditional FPGA fabric, encompassing enhanced layout, clocking, and slice capabilities
NoC Resources – Overview for Versal Adaptive SoC communication backplane, data-transfer, DDR controller
Enhanced DSP58 – New features, layout and operational modes for PL fabric-based DSP building blocks
AIE Vector Datatypes – Declaring vector datatypes required for the high-performance SIMD data-paths
Intrinsic(s) Coding – Introduction to proprietary syntax for maximizing AI engine vector processing
FIR Filter Coding for AIE – A step-by-step working example for 1GHz+ FIR filter targeting AI engine
Please come prepared to actively participate and engage directly with the workshop facilitator.
This workshop is delivered in 2 half-day sessions of interactive training comprising presentations with Q&A.
The workshops have kindly been sponsored by AMD Xilinx, and are available to attend FREE OF CHARGE.
Usual value of this training is $990 / €840
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Enquiry FormPrice on request