PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content as a scheduled in-person class and delivers comparable learning outcomes. Please note for this course, daily sessions are up to 7 hours including breaks.
The Arm® Cortex®-A55 is the next generation of low-power application processors from arm. It departs from the original Cortex-A53/A57/72/35 architecture with a completely new system architecture called DynamIQ. The DynamIQ architecture is also used for the latest cores such as the Cortex-A76.
This class is structured around three main topics:
Two thirds of this class is Arm material focussing primarily on the processor's details, the remaining part is provided by Doulos to augment the value of the content and provide a more rounded training class.
C programming for Embedded Systems training is also available from Doulos.
A carefully crafted combination of content from Arm and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.
Training material includes fully indexed course notes creating a complete reference manual.
Privilege levels • AArch64 registers • A64 Instruction Set • AArch64 Exception Model • AArch64 Memory Model
Cortex-A55 overview • Caches organization • Caches policies • Cache configuration • Translation lookaside buffer specifications • Memory prefetch • Non-temporal loads/stores • ECC and parity error detection
Registers • Loads and stores • Data processing and control flow • Scalar floating-point and SIMD • Armv8.2
Synchronization background • Enforced atomicity • Measured atomicity • Local and global exclusive monitors
The AArch64 exception model • Interrupts • Synchronous exceptions •
SError • exceptions • Exceptions in EL2 and EL3
Booting an ARM DynamIQ processor in AArch64 • Booting multi-core and multi-processor systems • Real-world booting
General Cache Information • Cache Attributes • Cache Maintenance Operations • Cache Discovery
Memory Management theory • Stage 1 Translations at EL1/0 • Translations at EL2 / EL3 • TLB maintenance
Types • Attributes • Alignment and endianness • Upper page descriptor bits
Data barriers • Instruction barriers • DynamIQ and Neoverse extensions
Why do we need a Secure environment? • Software stack • System architecture
Introduction to coherency • Coherency details - multi-core processors • Coherency details - multi-processor systems
Introduction • ARMv8-A Recap • Virtualization Host Extensions
DynamIQ Shared Unit • CPU bridges • CPU Caches • DSU snoop filter and L3 • L3 Cache allocation • DSU memory interfaces • Debug and trace • Power management
Semihosting / retargeting • Mixing C/C++ and assembly • Application Startup • Tailoring image memory map to your target • Accessing memory mapped peripherals • Additional considerations
Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data Issues
Introduction • Performance Monitoring Hardware: PMU • Cycle Accurate Trace: Trace • Macrocells • Streamline Performance Analysis
Linking Basics • System and User Libraries • Linker Script • Veneer and Interworking • Linker Optimizations and Diagnostics • GNU Embedded Development Libraries
Introduction to Debug • Types of Debug • Debug Facilities • External Debug • Self-hosted Debug • CoreSight • Debug Features • Trace
The learning is reinforced with unique Lab Exercises using an Armv8-A 64 bit instruction set simulator and covering assembly programming, exception handling and setting up the caches and MMU.
Complete an enquiry form and a Doulos representative will get back to you.
Enquiry FormPrice on request