Arm Cortex-A55 MPCore Software Design

• Software engineers who will be working with 8th generation Arm Cortex-A processors, in particular the Cortex-A55.
• Additionally, verification engineers who intend to write test-cases for a Cortex-A.

• Basic understanding of microprocessors
• Basic knowledge of the C programming language

C programming for Embedded Systems training is also available from Doulos.

A carefully crafted combination of content from Arm and Doulos will be used to provide exhaustive coverage of all of the essential topics required to achieve the learning objectives.

 

Architecture Overview

Privilege levels • AArch64 registers • A64 Instruction Set • AArch64 Exception Model • AArch64 Memory Model

Software Engineer's Cortex-A55

Cortex-A55 overview • Caches organization • Caches policies • Cache configuration • Translation lookaside buffer specifications • Memory prefetch • Non-temporal loads/stores • ECC and parity error detection

DynamIQ ISA Overview

Registers • Loads and stores • Data processing and control flow • Scalar floating-point and SIMD • Armv8.2

Synchronization

Synchronization background • Enforced atomicity • Measured atomicity • Local and global exclusive monitors

AArch64 Exception Model

The AArch64 exception model • Interrupts • Synchronous exceptions • 
SError • exceptions  • Exceptions in EL2 and EL3

Booting

Booting an Arm DynamIQ processor in AArch64 • Booting multi-core and multi-processor systems • Real-world booting

DynamIQ Caches and Branch Prediction

General Cache Information • Cache Attributes • Cache Maintenance Operations • Cache Discovery

DynamIQ Memory Management

Memory Management theory • Stage 1 Translations at EL1/0 • Translations at EL2 / EL3 • TLB maintenance

DynamIQ and Neoverse Memory Model

Types • Attributes • Alignment and endianness • Upper page descriptor bits

DynamIQ and Neoverse Barriers

Data barriers • Instruction barriers • DynamIQ and Neoverse extensions

Secure Environments

Why do we need a Secure environment? • Software stack • System architecture

DynamIQ Cache Coherency

Introduction to coherency • Coherency details - multi-core processors • Coherency details - multi-processor systems

Virtualization

Introduction • Armv8-A Recap • Virtualization Host Extensions

Software Engineer Guide to DynamIQ Shared Unit (DSU)

DynamIQ Shared Unit • CPU bridges • CPU Caches • DSU snoop filter and L3 • L3 Cache allocation • DSU memory interfaces • Debug and trace • Power management

Embedded Software Development

Semihosting / retargeting • Mixing C/C++ and assembly • Application Startup • Tailoring image memory map to your target • Accessing memory mapped peripherals • Additional considerations

GNU Compiler Hints and Tips

Basic Compilation • Compiler Optimizations • Coding Considerations • Local and Global Data Issues

NEON Benchmarking and Performance Analysis

Introduction • Performance Monitoring Hardware: PMU • Cycle Accurate Trace: Trace • Macrocells • Streamline Performance Analysis

Appendices 
(Optional material that can replace other content if required)

GNU Linker Hints and Tips

Linking Basics • System and User Libraries • Linker Script • Veneer and Interworking • Linker Optimizations and Diagnostics • GNU Embedded Development Libraries

Armv8-A Debug

Introduction to Debug • Types of Debug • Debug Facilities • External Debug • Self-hosted Debug • CoreSight • Debug Features • Trace

The learning is reinforced with unique Lab Exercises using an Armv8-A 64 bit instruction set simulator and covering assembly programming, exception handling and setting up the caches and MMU.

• Lab exercises for assembly programming cover the concepts of data processing, flow control, and rely on the GNU development tool-set.
• Exception handling lab exercises look at setting up various exception levels vector table and execution modes as well as executing hypervisor and secure calls.
• The Memory management lab takes you though the steps involved in implementing a typical system memory configuration using the MMU.
• The performance monitoring unit lab takes you through the steps required to configure and enable performance monitoring inside your processor.