AMD - PCIe Protocol Overview

Find a Training Course

AMD - PCIe Protocol Overview

Training Duration: 1 day

Course Description

This course focuses on the fundamentals of the PCI Express® protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered. Interrupts and error handling are also discussed.

Who Should Attend?

FPGA designers, logic designers and anyone who needs an in-depth knowledge of the PCIe protocol

Prerequisites

None

Software Tools

None required
VCD viewer optional

Hardware

Architecture: N/A*
Demo board: None*

* This course does not focus on any particular architecture. Please contact Doulos for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

Interpret various transactions occurring on the link
Describe the layered architecture and the tasks and packet types each is responsible for
Properly estimate maximum performance of a link
Illustrate how errors can be communicated within the system
Explain the relationship between Virtual Channels (VCs) and Traffic Class (TC) and the interaction with flow control credits

Course Outline

Introduction
Introduction to the PCIe Architecture
Review of the PCIe Protocol
Packet Formatting Details
Lab 1: Packet Decoding
Packet Routing
Interrupts and Error Management
Summary

Lab Descriptions

Lab 1: Packet Decoding – This lab explores what really happens on the link between a root complex and the endpoint. Various packets, including the Physical Layer, Data Link Layer, and Transaction Layer packets are explored. Insight as to what is actually transpiring on the lanes becomes a powerful tool for understanding the protocol as well as debugging various link issues.

Looking for team-based training, or other locations?

Complete an enquiry form and a Doulos representative will get back to you.

Enquiry FormPrice on request

PCIe Protocol Overview

Find a Training Course